t7406 & t7407: add missing && at end of lines
Signed-off-by: Jens Lehmann <Jens.Lehmann@web.de> Signed-off-by: Junio C Hamano <gitster@pobox.com>
Jens Lehmann committed
Sep 1, 2010 at 23:28 UTC
4bf9dd97827bf6f475a52e8f621dad24a3db9b4c
2 files changed
+3
-3
t/t7406-submodule-update.sh
+1
-1
@@ -25,7 +25,7 @@ test_expect_success 'setup a submodule tree' '
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echo file > file &&
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git add file &&
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test_tick &&
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- git commit -m upstream
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+ git commit -m upstream &&
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git clone . super &&
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git clone super submodule &&
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git clone super rebasing &&
t/t7407-submodule-foreach.sh
+2
-2
@@ -16,7 +16,7 @@ test_expect_success 'setup a submodule tree' '
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echo file > file &&
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git add file &&
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test_tick &&
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- git commit -m upstream
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+ git commit -m upstream &&
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git clone . super &&
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git clone super submodule &&
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(
@@ -30,7 +30,7 @@ test_expect_success 'setup a submodule tree' '
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submodule.sub2 submodule.foo2 &&
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git config -f .gitmodules --rename-section \
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submodule.sub3 submodule.foo3 &&
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- git add .gitmodules
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+ git add .gitmodules &&
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test_tick &&
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git commit -m "submodules" &&
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git submodule init sub1 &&