@samitouri / QOSamiQemu / commits / 002749d230

target/riscv/gdbstub.c: isolate TCG only checks

The following functions are TCG only and are broken, if they were ever usable in the first place, with KVM: - riscv_gdb_(get|se)t_csr - riscv_gdb_(get|set)_virtual - riscv_gen_dynamic_csr_feature Gate everything with TCG enabled to at least get them out of the way to enable --disable-tcg. As a note for the future: other archs have distincts gdbstub files for each accelerator. There's a strong case for RISC-V to do the same. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-ID: <20260703180538.3346781-20-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Daniel Henrique Barboza committed Jul 3, 2026 at 15:05 UTC 002749d230f63ba32d24a3139b69e86fe8f0c808

1 file changed +7 -1

target/riscv/gdbstub.c

+7 -1

@@ -164,6 +164,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n)

164 return 0;

165 }

166

167 +#ifdef CONFIG_TCG

168 static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n)

169 {

170 RISCVCPU *cpu = RISCV_CPU(cs);

@@ -294,6 +295,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)

295

296 return &cpu->dyn_csr_feature;

297 }

298 +#endif /* CONFIG_TCG */

299

300 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)

301 {

@@ -336,7 +338,6 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)

338

339 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)

340 {

339 - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);

341 RISCVCPU *cpu = RISCV_CPU(cs);

342 CPURISCVState *env = &cpu->env;

343 if (env->misa_ext & RVD) {

@@ -351,6 +352,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)

352 riscv_gdb_set_vector,

353 ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs));

354 }

355 +

356 +#ifdef CONFIG_TCG

357 + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);

358 +

359 switch (mcc->def->misa_mxl_max) {

360 case MXL_RV32:

361 gdb_register_coprocessor(cs, riscv_gdb_get_virtual,

@@ -371,4 +376,5 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)

376 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,

377 riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs));

378 }

379 +#endif

380 }