target/hexagon: add v68 HVX IEEE float conversion insns
Add HVX IEEE floating-point conversion instructions: - vconv_hf_h, vconv_h_hf, vconv_sf_w, vconv_w_sf: vconv operations - vcvt_hf_sf, vcvt_sf_hf: float <-> half float conversions - vcvt_hf_b, vcvt_hf_h, vcvt_hf_ub, vcvt_hf_uh: int to half float - vcvt_b_hf, vcvt_h_hf, vcvt_ub_hf, vcvt_uh_hf: half float to int Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/beca620d2e5e0bc15886bf967ab3961a49eca5f7.1776339451.git.matheus.bernardino@oss.qualcomm.com Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Matheus Tavares Bernardino committed
Apr 16, 2026 at 04:38 UTC
011b2512f9551b9c91d760fc38d65e5eb7bc2b3b
4 files changed
+137
target/hexagon/imported/mmvec/encode_ext.def
+18
@@ -840,4 +840,22 @@ DEF_ENC(V6_vfneg_sf,"00011110--0-0110PP1uuuuu011ddddd")
840
DEF_ENC(V6_vabs_hf,"00011110--0-0110PP1uuuuu100ddddd")
841
DEF_ENC(V6_vabs_sf,"00011110--0-0110PP1uuuuu101ddddd")
842
843
+/* IEEE FP vcvt instructions */
844
+DEF_ENC(V6_vcvt_sf_hf,"00011110--0-0100PP1uuuuu100ddddd")
845
+DEF_ENC(V6_vcvt_hf_sf,"00011111011vvvvvPP1uuuuu001ddddd")
846
+DEF_ENC(V6_vcvt_hf_ub,"00011110--0-0100PP1uuuuu001ddddd")
847
+DEF_ENC(V6_vcvt_hf_b,"00011110--0-0100PP1uuuuu010ddddd")
848
+DEF_ENC(V6_vcvt_hf_uh,"00011110--0-0100PP1uuuuu101ddddd")
849
+DEF_ENC(V6_vcvt_hf_h,"00011110--0-0100PP1uuuuu111ddddd")
850
+DEF_ENC(V6_vcvt_uh_hf,"00011110--0--101PP1uuuuu000ddddd")
851
+DEF_ENC(V6_vcvt_h_hf,"00011110--0-0110PP1uuuuu000ddddd")
852
+DEF_ENC(V6_vcvt_ub_hf,"00011111110vvvvvPP1uuuuu101ddddd")
853
+DEF_ENC(V6_vcvt_b_hf,"00011111110vvvvvPP1uuuuu110ddddd")
854
+
855
+/* IEEE FP vconv instructions */
856
+DEF_ENC(V6_vconv_sf_w,"00011110--0--101PP1uuuuu011ddddd")
857
+DEF_ENC(V6_vconv_w_sf,"00011110--0--101PP1uuuuu001ddddd")
858
+DEF_ENC(V6_vconv_hf_h,"00011110--0--101PP1uuuuu100ddddd")
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+DEF_ENC(V6_vconv_h_hf,"00011110--0--101PP1uuuuu010ddddd")
860
+
861
#endif /* NO MMVEC */
target/hexagon/imported/mmvec/ext.idef
+97
@@ -63,6 +63,9 @@ ITERATOR_INSN_ANY_SLOT_DOUBLE_VEC(WIDTH,TAG,SYNTAX2,DESCR,CODE)
63
EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS), \
64
DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))
65
66
+#define ITERATOR_INSN_SHIFT_SLOT_FLT(WIDTH,TAG,SYNTAX,DESCR,CODE) \
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+EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_HVX_FLT), \
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+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))
69
70
#define ITERATOR_INSN_SHIFT3_SLOT(WIDTH,TAG,SYNTAX,DESCR,CODE) \
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EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_CVI_VS_3SRC,A_NOTE_SHIFT_RESOURCE,A_NOTE_NOVP,A_NOTE_VA_UNARY), \
@@ -3046,6 +3049,100 @@ ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, "Vd32.hf=vabs(Vu32.hf)", \
3049
ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, "Vd32.sf=vabs(Vu32.sf)", \
3050
"Vector IEEE abs: sf", VdV.sf[i] = float32_abs(VuV.sf[i]))
3051
3052
+/* Two pipes: P2 & P3, two outputs, 16-bit */
3053
+#define ITERATOR_INSN_IEEE_FP_DOUBLE_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \
3054
+EXTINSN(V6_##TAG, SYNTAX, \
3055
+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_16), \
3056
+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))
3057
+
3058
+/* Two pipes: P2 & P3, two outputs, 32-bit output */
3059
+#define ITERATOR_INSN_IEEE_FP_DOUBLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \
3060
+EXTINSN(V6_##TAG, SYNTAX, \
3061
+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32), \
3062
+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))
3063
+
3064
+/* Single pipe, 16-bit output */
3065
+#define ITERATOR_INSN_IEEE_FP_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \
3066
+EXTINSN(V6_##TAG, SYNTAX, \
3067
+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16), \
3068
+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))
3069
+
3070
+/* single pipe, output can feed 16- or 32-bit accumulate */
3071
+#define ITERATOR_INSN_IEEE_FP_16_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \
3072
+EXTINSN(V6_##TAG, SYNTAX, \
3073
+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16,A_HVX_IEEE_FP_OUT_32), \
3074
+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))
3075
+
3076
+/******************************************************************************
3077
+ * IEEE FP convert instructions
3078
+ ******************************************************************************/
3079
+
3080
+ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_ub, "Vdd32.hf=vcvt(Vu32.ub)",
3081
+ "Vector IEEE cvt from int: ub widen to hf",
3082
+ VddV.v[0].hf[2*i] = uint64_to_float16_scalbn(VuV.ub[4*i], float_round_nearest_even, 0);
3083
+ VddV.v[0].hf[2*i+1] = uint64_to_float16_scalbn(VuV.ub[4*i+1], float_round_nearest_even, 0);
3084
+ VddV.v[1].hf[2*i] = uint64_to_float16_scalbn(VuV.ub[4*i+2], float_round_nearest_even, 0);
3085
+ VddV.v[1].hf[2*i+1] = uint64_to_float16_scalbn(VuV.ub[4*i+3], float_round_nearest_even, 0))
3086
+
3087
+ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_b, "Vdd32.hf=vcvt(Vu32.b)",
3088
+ "Vector IEEE cvt from int: b widen to hf",
3089
+ VddV.v[0].hf[2*i] = int64_to_float16_scalbn(VuV.b[4*i], float_round_nearest_even, 0);
3090
+ VddV.v[0].hf[2*i+1] = int64_to_float16_scalbn(VuV.b[4*i+1], float_round_nearest_even, 0);
3091
+ VddV.v[1].hf[2*i] = int64_to_float16_scalbn(VuV.b[4*i+2], float_round_nearest_even, 0);
3092
+ VddV.v[1].hf[2*i+1] = int64_to_float16_scalbn(VuV.b[4*i+3], float_round_nearest_even, 0))
3093
+
3094
+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vcvt_sf_hf, "Vdd32.sf=vcvt(Vu32.hf)",
3095
+ "Vector IEEE cvt: hf widen to sf",
3096
+ VddV.v[0].sf[i] = f16_to_f32(VuV.hf[2*i]);
3097
+ VddV.v[1].sf[i] = f16_to_f32(VuV.hf[2*i+1]))
3098
+
3099
+ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_uh, "Vd32.hf=vcvt(Vu32.uh)",
3100
+ "Vector IEEE cvt from int: uh to hf",
3101
+ VdV.hf[i] = uint64_to_float16_scalbn(VuV.uh[i], float_round_nearest_even, 0))
3102
+ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_h, "Vd32.hf=vcvt(Vu32.h)",
3103
+ "Vector IEEE cvt from int: h to hf",
3104
+ VdV.hf[i] = int64_to_float16_scalbn(VuV.h[i], float_round_nearest_even, 0))
3105
+ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_uh_hf, "Vd32.uh=vcvt(Vu32.hf)",
3106
+ "Vector IEEE cvt to int: hf to uh",
3107
+ VdV.uh[i] = float16_to_uint16_scalbn(VuV.hf[i], float_round_nearest_even, 0, &env->hvx_fp_status))
3108
+ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_h_hf, "Vd32.h=vcvt(Vu32.hf)",
3109
+ "Vector IEEE cvt to int: hf to h",
3110
+ VdV.h[i] = float16_to_int16_scalbn(VuV.hf[i], float_round_nearest_even, 0, &env->hvx_fp_status))
3111
+
3112
+ITERATOR_INSN_IEEE_FP_16(32, vcvt_hf_sf, "Vd32.hf=vcvt(Vu32.sf,Vv32.sf)",
3113
+ "Vector IEEE cvt: sf to hf",
3114
+ VdV.hf[2*i] = f32_to_f16(VuV.sf[i]);
3115
+ VdV.hf[2*i+1] = f32_to_f16(VvV.sf[i]))
3116
+
3117
+ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_ub_hf, "Vd32.ub=vcvt(Vu32.hf,Vv32.hf)", "Vector cvt to int: hf narrow to ub",
3118
+ VdV.ub[4*i] = float16_to_uint8_scalbn(VuV.hf[2*i], float_round_nearest_even, 0, &env->hvx_fp_status);
3119
+ VdV.ub[4*i+1] = float16_to_uint8_scalbn(VuV.hf[2*i+1], float_round_nearest_even, 0, &env->hvx_fp_status);
3120
+ VdV.ub[4*i+2] = float16_to_uint8_scalbn(VvV.hf[2*i], float_round_nearest_even, 0, &env->hvx_fp_status);
3121
+ VdV.ub[4*i+3] = float16_to_uint8_scalbn(VvV.hf[2*i+1], float_round_nearest_even, 0, &env->hvx_fp_status))
3122
+
3123
+ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_b_hf, "Vd32.b=vcvt(Vu32.hf,Vv32.hf)",
3124
+ "Vector cvt to int: hf narrow to b",
3125
+ VdV.b[4*i] = float16_to_int8_scalbn(VuV.hf[2*i], float_round_nearest_even, 0, &env->hvx_fp_status);
3126
+ VdV.b[4*i+1] = float16_to_int8_scalbn(VuV.hf[2*i+1], float_round_nearest_even, 0, &env->hvx_fp_status);
3127
+ VdV.b[4*i+2] = float16_to_int8_scalbn(VvV.hf[2*i], float_round_nearest_even, 0, &env->hvx_fp_status);
3128
+ VdV.b[4*i+3] = float16_to_int8_scalbn(VvV.hf[2*i+1], float_round_nearest_even, 0, &env->hvx_fp_status))
3129
+
3130
+ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_w_sf,"Vd32.w=Vu32.sf",
3131
+ "Vector conversion of sf32 format to int w",
3132
+ VdV.w[i] = conv_w_sf(VuV.sf[i], &env->hvx_fp_status))
3133
+
3134
+ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h_hf,"Vd32.h=Vu32.hf",
3135
+ "Vector conversion of hf16 format to int hw",
3136
+ VdV.h[i] = conv_h_hf(VuV.hf[i], &env->hvx_fp_status))
3137
+
3138
+ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_sf_w,"Vd32.sf=Vu32.w",
3139
+ "Vector conversion of int w format to sf32",
3140
+ VdV.sf[i] = int32_to_float32(VuV.w[i], &env->hvx_fp_status))
3141
+
3142
+ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,"Vd32.hf=Vu32.h",
3143
+ "Vector conversion of int hw format to hf16",
3144
+ VdV.hf[i] = float16_val(int16_to_float16(VuV.h[i], &env->hvx_fp_status)))
3145
+
3146
/******************************************************************************
3147
DEBUG Vector/Register Printing
3148
******************************************************************************/
target/hexagon/mmvec/hvx_ieee_fp.c
+18
@@ -69,3 +69,21 @@ float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status)
69
}
70
return float16_min(a1, a2, fp_status);
71
}
72
+
73
+int32_t conv_w_sf(float32 a, float_status *fp_status)
74
+{
75
+ /* float32_to_int32 converts any NaN to MAX, hexagon looks at the sign. */
76
+ if (float32_is_any_nan(a)) {
77
+ return float32_is_neg(a) ? INT32_MIN : INT32_MAX;
78
+ }
79
+ return float32_to_int32_round_to_zero(a, fp_status);
80
+}
81
+
82
+int16_t conv_h_hf(float16 a, float_status *fp_status)
83
+{
84
+ /* float16_to_int16 converts any NaN to MAX, hexagon looks at the sign. */
85
+ if (float16_is_any_nan(a)) {
86
+ return float16_is_neg(a) ? INT16_MIN : INT16_MAX;
87
+ }
88
+ return float16_to_int16_round_to_zero(a, fp_status);
89
+}
target/hexagon/mmvec/hvx_ieee_fp.h
+4
@@ -10,6 +10,7 @@
10
#include "fpu/softfloat.h"
11
12
#define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status)
13
+#define f32_to_f16(A) float32_to_float16((A), true, &env->hvx_fp_status)
14
15
float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status);
16
float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,
@@ -21,4 +22,7 @@ float32 qf_min_sf(float32 a1, float32 a2, float_status *fp_status);
22
float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status);
23
float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status);
24
25
+int32_t conv_w_sf(float32 a, float_status *fp_status);
26
+int16_t conv_h_hf(float16 a, float_status *fp_status);
27
+
28
#endif