target/arm: Implement Floating-point convert (predicated, zeroing)
This is FCVTX, FCVT and BFCVT. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260604234852.573178-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 4, 2026 at 16:48 UTC
03e944fbfe2e361441dd1b9c2d53d1aed87e450f
2 files changed
+33
target/arm/tcg/sve.decode
+11
@@ -1215,6 +1215,17 @@ FCVT_hd_m 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0
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FCVT_ds_m 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
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FCVT_sd_m 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
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+FCVTX_ds_z 01100100 00 0110 101 10 ... ..... ..... @rd_pg_rn_e0
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+
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+FCVT_sh_z 01100100 10 0110 101 00 ... ..... ..... @rd_pg_rn_e0
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+FCVT_hs_z 01100100 10 0110 101 01 ... ..... ..... @rd_pg_rn_e0
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+BFCVT_z 01100100 10 0110 101 10 ... ..... ..... @rd_pg_rn_e0
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+
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+FCVT_dh_z 01100100 11 0110 101 00 ... ..... ..... @rd_pg_rn_e0
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+FCVT_hd_z 01100100 11 0110 101 01 ... ..... ..... @rd_pg_rn_e0
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+FCVT_ds_z 01100100 11 0110 101 10 ... ..... ..... @rd_pg_rn_e0
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+FCVT_sd_z 01100100 11 0110 101 11 ... ..... ..... @rd_pg_rn_e0
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+
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# SVE floating-point convert to integer
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FCVTZS_hh_m 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0
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FCVTZU_hh_m 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0
target/arm/tcg/translate-sve.c
+22
@@ -4588,21 +4588,40 @@ TRANS_FEAT(FCMLA_zzxz, aa64_sme_or_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz
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TRANS_FEAT(FCVT_sh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_fcvt_sh, a, 0, FPST_A64)
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+TRANS_FEAT(FCVT_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvt_sh, a, 1, FPST_A64)
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+
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TRANS_FEAT(FCVT_hs_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16)
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+TRANS_FEAT(FCVT_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvt_hs, a, 1, FPST_A64_F16)
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TRANS_FEAT(BFCVT_m, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_bfcvt, a, 0,
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s->fpcr_ah ? FPST_AH : FPST_A64)
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+TRANS_FEAT(BFCVT_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_bfcvt, a, 1,
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+ s->fpcr_ah ? FPST_AH : FPST_A64)
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TRANS_FEAT(FCVT_dh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_fcvt_dh, a, 0, FPST_A64)
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+TRANS_FEAT(FCVT_dh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvt_dh, a, 1, FPST_A64)
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+
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TRANS_FEAT(FCVT_hd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_fcvt_hd, a, 0, FPST_A64_F16)
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+TRANS_FEAT(FCVT_hd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvt_hd, a, 1, FPST_A64_F16)
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+
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TRANS_FEAT(FCVT_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_fcvt_ds, a, 0, FPST_A64)
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+TRANS_FEAT(FCVT_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvt_ds, a, 1, FPST_A64)
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+
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TRANS_FEAT(FCVT_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_fcvt_sd, a, 0, FPST_A64)
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+TRANS_FEAT(FCVT_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
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+ gen_helper_sve_fcvt_sd, a, 1, FPST_A64)
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TRANS_FEAT(FCVTZS_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
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gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16)
@@ -8017,6 +8036,9 @@ TRANS_FEAT(FCVTLT_sd_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
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TRANS_FEAT(FCVTX_ds_m, aa64_sme_or_sve2, do_frint_mode, a,
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FPROUNDING_ODD, 0, gen_helper_sve_fcvt_ds)
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+TRANS_FEAT(FCVTX_ds_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a,
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+ FPROUNDING_ODD, 1, gen_helper_sve_fcvt_ds)
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+
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TRANS_FEAT(FCVTXNT_ds_m, aa64_sme_or_sve2, do_frint_mode, a,
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FPROUNDING_ODD, 0, gen_helper_sve2_fcvtnt_ds)
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