@samitouri / QOSamiQemu / commits / 072ddc8eb9

hw/net: Remove the xgmac device

The xgmac device was only used by the highbank machine that just has been removed. Being a sysbus device that cannot be instantiated by the user, this is dead code now and thus can be removed, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Thomas Huth committed Mar 6, 2026 at 09:01 UTC 072ddc8eb97581a6800eb6d8d864b28102c46280
4 files changed +1 -448
hw/net/Kconfig
-3
@@ -79,9 +79,6 @@ config NE2000_ISA
79 config OPENCORES_ETH
80 bool
81
82 -config XGMAC
83 - bool
84 -
82 config ALLWINNER_EMAC
83 bool
84
hw/net/meson.build
-1
@@ -22,7 +22,6 @@ system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
22 system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
23 system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
24 system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
25 -system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
25 system_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('xilinx_axienet.c'))
26 system_ss.add(when: 'CONFIG_ALLWINNER_EMAC', if_true: files('allwinner_emac.c'))
27 system_ss.add(when: 'CONFIG_ALLWINNER_SUN8I_EMAC', if_true: files('allwinner-sun8i-emac.c'))
hw/net/xgmac.c deleted
-443
@@ -1,443 +0,0 @@
1 -/*
2 - * QEMU model of XGMAC Ethernet.
3 - *
4 - * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
5 - *
6 - * Copyright (c) 2011 Calxeda, Inc.
7 - *
8 - * Permission is hereby granted, free of charge, to any person obtaining a copy
9 - * of this software and associated documentation files (the "Software"), to deal
10 - * in the Software without restriction, including without limitation the rights
11 - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 - * copies of the Software, and to permit persons to whom the Software is
13 - * furnished to do so, subject to the following conditions:
14 - *
15 - * The above copyright notice and this permission notice shall be included in
16 - * all copies or substantial portions of the Software.
17 - *
18 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 - * THE SOFTWARE.
25 - */
26 -
27 -#include "qemu/osdep.h"
28 -#include "hw/core/irq.h"
29 -#include "hw/core/qdev-properties.h"
30 -#include "hw/core/sysbus.h"
31 -#include "exec/cpu-common.h"
32 -#include "migration/vmstate.h"
33 -#include "qemu/module.h"
34 -#include "net/net.h"
35 -#include "qom/object.h"
36 -
37 -#ifdef DEBUG_XGMAC
38 -#define DEBUGF_BRK(message, args...) do { \
39 - fprintf(stderr, (message), ## args); \
40 - } while (0)
41 -#else
42 -#define DEBUGF_BRK(message, args...) do { } while (0)
43 -#endif
44 -
45 -#define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
46 -#define XGMAC_FRAME_FILTER 0x00000001 /* MAC Frame Filter */
47 -#define XGMAC_FLOW_CTRL 0x00000006 /* MAC Flow Control */
48 -#define XGMAC_VLAN_TAG 0x00000007 /* VLAN Tags */
49 -#define XGMAC_VERSION 0x00000008 /* Version */
50 -/* VLAN tag for insertion or replacement into tx frames */
51 -#define XGMAC_VLAN_INCL 0x00000009
52 -#define XGMAC_LPI_CTRL 0x0000000a /* LPI Control and Status */
53 -#define XGMAC_LPI_TIMER 0x0000000b /* LPI Timers Control */
54 -#define XGMAC_TX_PACE 0x0000000c /* Transmit Pace and Stretch */
55 -#define XGMAC_VLAN_HASH 0x0000000d /* VLAN Hash Table */
56 -#define XGMAC_DEBUG 0x0000000e /* Debug */
57 -#define XGMAC_INT_STATUS 0x0000000f /* Interrupt and Control */
58 -/* HASH table registers */
59 -#define XGMAC_HASH(n) ((0x00000300/4) + (n))
60 -#define XGMAC_NUM_HASH 16
61 -/* Operation Mode */
62 -#define XGMAC_OPMODE (0x00000400/4)
63 -/* Remote Wake-Up Frame Filter */
64 -#define XGMAC_REMOTE_WAKE (0x00000700/4)
65 -/* PMT Control and Status */
66 -#define XGMAC_PMT (0x00000704/4)
67 -
68 -#define XGMAC_ADDR_HIGH(reg) (0x00000010+((reg) * 2))
69 -#define XGMAC_ADDR_LOW(reg) (0x00000011+((reg) * 2))
70 -
71 -#define DMA_BUS_MODE 0x000003c0 /* Bus Mode */
72 -#define DMA_XMT_POLL_DEMAND 0x000003c1 /* Transmit Poll Demand */
73 -#define DMA_RCV_POLL_DEMAND 0x000003c2 /* Received Poll Demand */
74 -#define DMA_RCV_BASE_ADDR 0x000003c3 /* Receive List Base */
75 -#define DMA_TX_BASE_ADDR 0x000003c4 /* Transmit List Base */
76 -#define DMA_STATUS 0x000003c5 /* Status Register */
77 -#define DMA_CONTROL 0x000003c6 /* Ctrl (Operational Mode) */
78 -#define DMA_INTR_ENA 0x000003c7 /* Interrupt Enable */
79 -#define DMA_MISSED_FRAME_CTR 0x000003c8 /* Missed Frame Counter */
80 -/* Receive Interrupt Watchdog Timer */
81 -#define DMA_RI_WATCHDOG_TIMER 0x000003c9
82 -#define DMA_AXI_BUS 0x000003ca /* AXI Bus Mode */
83 -#define DMA_AXI_STATUS 0x000003cb /* AXI Status */
84 -#define DMA_CUR_TX_DESC_ADDR 0x000003d2 /* Current Host Tx Descriptor */
85 -#define DMA_CUR_RX_DESC_ADDR 0x000003d3 /* Current Host Rx Descriptor */
86 -#define DMA_CUR_TX_BUF_ADDR 0x000003d4 /* Current Host Tx Buffer */
87 -#define DMA_CUR_RX_BUF_ADDR 0x000003d5 /* Current Host Rx Buffer */
88 -#define DMA_HW_FEATURE 0x000003d6 /* Enabled Hardware Features */
89 -
90 -/* DMA Status register defines */
91 -#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
92 -#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
93 -#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
94 -#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
95 -#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
96 -#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
97 -#define DMA_STATUS_TS_SHIFT 20
98 -#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
99 -#define DMA_STATUS_RS_SHIFT 17
100 -#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
101 -#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
102 -#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
103 -#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
104 -#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
105 -#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
106 -#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
107 -#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
108 -#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
109 -#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
110 -#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
111 -#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
112 -#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
113 -#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
114 -#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
115 -
116 -/* DMA Control register defines */
117 -#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
118 -#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
119 -#define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
120 -
121 -struct desc {
122 - uint32_t ctl_stat;
123 - uint16_t buffer1_size;
124 - uint16_t buffer2_size;
125 - uint32_t buffer1_addr;
126 - uint32_t buffer2_addr;
127 - uint32_t ext_stat;
128 - uint32_t res[3];
129 -};
130 -
131 -#define R_MAX 0x400
132 -
133 -typedef struct RxTxStats {
134 - uint64_t rx_bytes;
135 - uint64_t tx_bytes;
136 -
137 - uint64_t rx;
138 - uint64_t rx_bcast;
139 - uint64_t rx_mcast;
140 -} RxTxStats;
141 -
142 -#define TYPE_XGMAC "xgmac"
143 -OBJECT_DECLARE_SIMPLE_TYPE(XgmacState, XGMAC)
144 -
145 -struct XgmacState {
146 - SysBusDevice parent_obj;
147 -
148 - MemoryRegion iomem;
149 - qemu_irq sbd_irq;
150 - qemu_irq pmt_irq;
151 - qemu_irq mci_irq;
152 - NICState *nic;
153 - NICConf conf;
154 -
155 - struct RxTxStats stats;
156 - uint32_t regs[R_MAX];
157 -};
158 -
159 -static const VMStateDescription vmstate_rxtx_stats = {
160 - .name = "xgmac_stats",
161 - .version_id = 1,
162 - .minimum_version_id = 1,
163 - .fields = (const VMStateField[]) {
164 - VMSTATE_UINT64(rx_bytes, RxTxStats),
165 - VMSTATE_UINT64(tx_bytes, RxTxStats),
166 - VMSTATE_UINT64(rx, RxTxStats),
167 - VMSTATE_UINT64(rx_bcast, RxTxStats),
168 - VMSTATE_UINT64(rx_mcast, RxTxStats),
169 - VMSTATE_END_OF_LIST()
170 - }
171 -};
172 -
173 -static const VMStateDescription vmstate_xgmac = {
174 - .name = "xgmac",
175 - .version_id = 1,
176 - .minimum_version_id = 1,
177 - .fields = (const VMStateField[]) {
178 - VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats),
179 - VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX),
180 - VMSTATE_END_OF_LIST()
181 - }
182 -};
183 -
184 -static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx)
185 -{
186 - uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] :
187 - s->regs[DMA_CUR_TX_DESC_ADDR];
188 - cpu_physical_memory_read(addr, d, sizeof(*d));
189 -}
190 -
191 -static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx)
192 -{
193 - int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR;
194 - uint32_t addr = s->regs[reg];
195 -
196 - if (!rx && (d->ctl_stat & 0x00200000)) {
197 - s->regs[reg] = s->regs[DMA_TX_BASE_ADDR];
198 - } else if (rx && (d->buffer1_size & 0x8000)) {
199 - s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR];
200 - } else {
201 - s->regs[reg] += sizeof(*d);
202 - }
203 - cpu_physical_memory_write(addr, d, sizeof(*d));
204 -}
205 -
206 -static void xgmac_enet_send(XgmacState *s)
207 -{
208 - struct desc bd;
209 - int frame_size;
210 - int len;
211 - QEMU_UNINITIALIZED uint8_t frame[8192];
212 - uint8_t *ptr;
213 -
214 - ptr = frame;
215 - frame_size = 0;
216 - while (1) {
217 - xgmac_read_desc(s, &bd, 0);
218 - if ((bd.ctl_stat & 0x80000000) == 0) {
219 - /* Run out of descriptors to transmit. */
220 - break;
221 - }
222 - len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff);
223 -
224 - /*
225 - * FIXME: these cases of malformed tx descriptors (bad sizes)
226 - * should probably be reported back to the guest somehow
227 - * rather than simply silently stopping processing, but we
228 - * don't know what the hardware does in this situation.
229 - * This will only happen for buggy guests anyway.
230 - */
231 - if ((bd.buffer1_size & 0xfff) > 2048) {
232 - DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
233 - "xgmac buffer 1 len on send > 2048 (0x%x)\n",
234 - __func__, bd.buffer1_size & 0xfff);
235 - break;
236 - }
237 - if ((bd.buffer2_size & 0xfff) != 0) {
238 - DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
239 - "xgmac buffer 2 len on send != 0 (0x%x)\n",
240 - __func__, bd.buffer2_size & 0xfff);
241 - break;
242 - }
243 - if (frame_size + len >= sizeof(frame)) {
244 - DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu "
245 - "buffer\n" , __func__, frame_size + len, sizeof(frame));
246 - DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n",
247 - __func__, bd.buffer1_size, bd.buffer2_size);
248 - break;
249 - }
250 -
251 - cpu_physical_memory_read(bd.buffer1_addr, ptr, len);
252 - ptr += len;
253 - frame_size += len;
254 - if (bd.ctl_stat & 0x20000000) {
255 - /* Last buffer in frame. */
256 - qemu_send_packet(qemu_get_queue(s->nic), frame, len);
257 - ptr = frame;
258 - frame_size = 0;
259 - s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS;
260 - }
261 - bd.ctl_stat &= ~0x80000000;
262 - /* Write back the modified descriptor. */
263 - xgmac_write_desc(s, &bd, 0);
264 - }
265 -}
266 -
267 -static void enet_update_irq(XgmacState *s)
268 -{
269 - int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA];
270 - qemu_set_irq(s->sbd_irq, !!stat);
271 -}
272 -
273 -static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
274 -{
275 - XgmacState *s = opaque;
276 - uint64_t r = 0;
277 - addr >>= 2;
278 -
279 - switch (addr) {
280 - case XGMAC_VERSION:
281 - r = 0x1012;
282 - break;
283 - default:
284 - if (addr < ARRAY_SIZE(s->regs)) {
285 - r = s->regs[addr];
286 - }
287 - break;
288 - }
289 - return r;
290 -}
291 -
292 -static void enet_write(void *opaque, hwaddr addr,
293 - uint64_t value, unsigned size)
294 -{
295 - XgmacState *s = opaque;
296 -
297 - addr >>= 2;
298 - switch (addr) {
299 - case DMA_BUS_MODE:
300 - s->regs[DMA_BUS_MODE] = value & ~0x1;
301 - break;
302 - case DMA_XMT_POLL_DEMAND:
303 - xgmac_enet_send(s);
304 - break;
305 - case DMA_STATUS:
306 - s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value;
307 - break;
308 - case DMA_RCV_BASE_ADDR:
309 - s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value;
310 - break;
311 - case DMA_TX_BASE_ADDR:
312 - s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value;
313 - break;
314 - default:
315 - if (addr < ARRAY_SIZE(s->regs)) {
316 - s->regs[addr] = value;
317 - }
318 - break;
319 - }
320 - enet_update_irq(s);
321 -}
322 -
323 -static const MemoryRegionOps enet_mem_ops = {
324 - .read = enet_read,
325 - .write = enet_write,
326 - .endianness = DEVICE_LITTLE_ENDIAN,
327 -};
328 -
329 -static int eth_can_rx(XgmacState *s)
330 -{
331 - /* RX enabled? */
332 - return s->regs[DMA_CONTROL] & DMA_CONTROL_SR;
333 -}
334 -
335 -static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
336 -{
337 - XgmacState *s = qemu_get_nic_opaque(nc);
338 - static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
339 - 0xff, 0xff, 0xff};
340 - int unicast, broadcast, multicast;
341 - struct desc bd;
342 - ssize_t ret;
343 -
344 - if (!eth_can_rx(s)) {
345 - return -1;
346 - }
347 - unicast = ~buf[0] & 0x1;
348 - broadcast = memcmp(buf, sa_bcast, 6) == 0;
349 - multicast = !unicast && !broadcast;
350 - if (size < 12) {
351 - s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
352 - ret = -1;
353 - goto out;
354 - }
355 -
356 - xgmac_read_desc(s, &bd, 1);
357 - if ((bd.ctl_stat & 0x80000000) == 0) {
358 - s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS;
359 - ret = size;
360 - goto out;
361 - }
362 -
363 - cpu_physical_memory_write(bd.buffer1_addr, buf, size);
364 -
365 - /* Add in the 4 bytes for crc (the real hw returns length incl crc) */
366 - size += 4;
367 - bd.ctl_stat = (size << 16) | 0x300;
368 - xgmac_write_desc(s, &bd, 1);
369 -
370 - s->stats.rx_bytes += size;
371 - s->stats.rx++;
372 - if (multicast) {
373 - s->stats.rx_mcast++;
374 - } else if (broadcast) {
375 - s->stats.rx_bcast++;
376 - }
377 -
378 - s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
379 - ret = size;
380 -
381 -out:
382 - enet_update_irq(s);
383 - return ret;
384 -}
385 -
386 -static NetClientInfo net_xgmac_enet_info = {
387 - .type = NET_CLIENT_DRIVER_NIC,
388 - .size = sizeof(NICState),
389 - .receive = eth_rx,
390 -};
391 -
392 -static void xgmac_enet_realize(DeviceState *dev, Error **errp)
393 -{
394 - SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
395 - XgmacState *s = XGMAC(dev);
396 -
397 - memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s,
398 - "xgmac", 0x1000);
399 - sysbus_init_mmio(sbd, &s->iomem);
400 - sysbus_init_irq(sbd, &s->sbd_irq);
401 - sysbus_init_irq(sbd, &s->pmt_irq);
402 - sysbus_init_irq(sbd, &s->mci_irq);
403 -
404 - qemu_macaddr_default_if_unset(&s->conf.macaddr);
405 - s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf,
406 - object_get_typename(OBJECT(dev)), dev->id,
407 - &dev->mem_reentrancy_guard, s);
408 - qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
409 -
410 - s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) |
411 - s->conf.macaddr.a[4];
412 - s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) |
413 - (s->conf.macaddr.a[2] << 16) |
414 - (s->conf.macaddr.a[1] << 8) |
415 - s->conf.macaddr.a[0];
416 -}
417 -
418 -static const Property xgmac_properties[] = {
419 - DEFINE_NIC_PROPERTIES(XgmacState, conf),
420 -};
421 -
422 -static void xgmac_enet_class_init(ObjectClass *klass, const void *data)
423 -{
424 - DeviceClass *dc = DEVICE_CLASS(klass);
425 -
426 - dc->realize = xgmac_enet_realize;
427 - dc->vmsd = &vmstate_xgmac;
428 - device_class_set_props(dc, xgmac_properties);
429 -}
430 -
431 -static const TypeInfo xgmac_enet_info = {
432 - .name = TYPE_XGMAC,
433 - .parent = TYPE_SYS_BUS_DEVICE,
434 - .instance_size = sizeof(XgmacState),
435 - .class_init = xgmac_enet_class_init,
436 -};
437 -
438 -static void xgmac_enet_register_types(void)
439 -{
440 - type_register_static(&xgmac_enet_info);
441 -}
442 -
443 -type_init(xgmac_enet_register_types)
scripts/coverity-scan/COMPONENTS.md
+1 -1
@@ -4,7 +4,7 @@ alpha
4 ~ .*/qemu((/include)?/hw/alpha/.*|/target/alpha/.*)
5
6 arm
7 - ~ .*/qemu((/include)?/hw/arm/.*|(/include)?/hw/.*/(arm|allwinner-a10|bcm28|digic|exynos|imx|omap|stellaris|pxa2xx|versatile|zynq|cadence).*|/hw/net/xgmac.c|/hw/ssi/xilinx_spips.c|/target/arm/.*)
7 + ~ .*/qemu((/include)?/hw/arm/.*|(/include)?/hw/.*/(arm|allwinner-a10|bcm28|digic|exynos|imx|omap|stellaris|pxa2xx|versatile|zynq|cadence).*|/hw/ssi/xilinx_spips.c|/target/arm/.*)
8
9 avr
10 ~ .*/qemu((/include)?/hw/avr/.*|/target/avr/.*)