docs/specs/fw_cfg: Document all architecture register layouts
We implement the fw_cfg device for more architectures and machines that we let on about in our documentation. Luckily most of the new ones (notably riscv and loongarch) have followed the straightforward layout that the Arm virt board picked. Restructure the documentation to present this as the "standard" layout, followed by the other layouts used by various other boards for historical reasons. This adds PA-RISC, SPARC, PPC and MIPS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-id: 20260529174639.451353-2-peter.maydell@linaro.org Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Peter Maydell committed
May 29, 2026 at 18:46 UTC
079466ae92ccf3206f6a7a939ff40aef04d8424e
1 file changed
+24
-4
docs/specs/fw_cfg.rst
+24
-4
@@ -84,15 +84,35 @@ increasing address order, similar to memcpy().
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Register Locations
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------------------
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+For a memory-mapped fw_cfg device, the standard register layout is:
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+
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+ * base address : Data Register (64 bit)
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+ * base address + 8 : Selector Register (16 bit)
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+ * base address + 16 : DMA Address Register (64 bit)
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+
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+Some architectures or machines have a different layout for historical reasons:
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+
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x86, x86_64
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* Selector Register IOport: 0x510
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* Data Register IOport: 0x511
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* DMA Address IOport: 0x514
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-Arm
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- * Selector Register address: Base + 8 (2 bytes)
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- * Data Register address: Base + 0 (8 bytes)
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- * DMA Address address: Base + 16 (8 bytes)
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+PA-RISC:
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+ * base address : Selector Register (16 bit)
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+ * base address + 4 : Data Register (8 bit)
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+
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+32-bit SPARC, PPC ``g3beige``, ``mac99``, ``prep``:
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+ * base address : Selector Register (16 bit)
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+ * base address + 2 : Data Register (8 bit)
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+
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+64-bit SPARC:
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+ * base address : Selector Register (16 bit)
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+ * base address + 1 : Data Register (8 bit)
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+
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+MIPS ``loongson3-virt`` machine:
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+ * base address : Selector Register (16 bit)
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+ * base address + 8 : Data Register (64 bit)
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+
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ACPI Interface
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