target/arm: Enable FEAT_FP8FMA, FEAT_SSVE_FP8FMA for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
07e9ea8f1c3e2af07f16ac263e3ca7dbcfb8d7a6
3 files changed
+6
docs/system/arm/emulation.rst
+2
@@ -76,6 +76,7 @@ the following architecture extensions:
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- FEAT_FP (Floating Point extensions)
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- FEAT_FP16 (Half-precision floating-point data processing)
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- FEAT_FP8 (FP8 convert instructions)
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+- FEAT_FP8FMA (FP8 multiply-accumulate to half-precision and single-precision instructions)
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- FEAT_FPAC (Faulting on AUT* instructions)
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- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
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- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions)
@@ -166,6 +167,7 @@ the following architecture extensions:
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- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
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- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
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- FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit elements)
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+- FEAT_SSVE_FP8FMA (SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode)
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- FEAT_SVE (Scalable Vector Extension)
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- FEAT_SVE_AES (Scalable Vector AES instructions)
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- FEAT_SVE_B16B16 (Non-widening BFloat16 arithmetic for SVE2)
linux-user/aarch64/elfload.c
+2
@@ -226,6 +226,8 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
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GET_FEATURE_ID(aa64_f8cvt, ARM_HWCAP2_A64_F8CVT |
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ARM_HWCAP2_A64_F8E4M3 |
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ARM_HWCAP2_A64_F8E5M2);
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+ GET_FEATURE_ID(aa64_f8fma, ARM_HWCAP2_A64_F8FMA);
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+ GET_FEATURE_ID(aa64_ssve_f8fma, ARM_HWCAP2_A64_SME_SF8FMA);
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return hwcaps;
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}
target/arm/tcg/cpu64.c
+2
@@ -1383,6 +1383,7 @@ void aarch64_max_tcg_initfn(Object *obj)
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SET_IDREG(isar, ID_AA64DFR0, t);
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t = GET_IDREG(isar, ID_AA64SMFR0);
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+ t = FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* FEAT_SSVE_FP8FMA */
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t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
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t = FIELD_DP64(t, ID_AA64SMFR0, BI32I32, 1); /* FEAT_SME2 */
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t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
@@ -1401,6 +1402,7 @@ void aarch64_max_tcg_initfn(Object *obj)
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t = GET_IDREG(isar, ID_AA64FPFR0);
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t = FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* FEAT_FP8 */
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t = FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* FEAT_FP8 */
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+ t = FIELD_DP64(t, ID_AA64FPFR0, F8FMA, 1); /* FEAT_FP8FMA */
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t = FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* FEAT_FP8 */
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SET_IDREG(isar, ID_AA64FPFR0, t);
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