target/arm: Implement FDOT (FP8 to FP16) for SVE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-39-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:21 UTC
0c00be3786c2b8441d20dd092276100f03deeb75
3 files changed
+42
target/arm/cpu-features.h
+5
@@ -1580,6 +1580,11 @@ static inline bool isar_feature_aa64_ssve_f8dp4(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8DP4);
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}
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+static inline bool isar_feature_aa64_ssve_f8dp2(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8DP2);
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+}
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+
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static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16);
target/arm/tcg/sve.decode
+2
@@ -1875,6 +1875,7 @@ FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
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BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
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FDOT_sb 01100100 01 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2
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+FDOT_hb 01100100 00 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=1
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### SVE2 floating-point multiply-add long (indexed)
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@@ -1900,6 +1901,7 @@ FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2
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BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2
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FDOT_idx_sb 01100100 01 1 ..... 010001 ..... ..... @rrxr_2 esz=2
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+FDOT_idx_hb 01100100 00 1 ..... 0100.1 ..... ..... @rrx_3a esz=1
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### SVE broadcast predicate element
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target/arm/tcg/translate-sve.c
+35
@@ -8426,3 +8426,38 @@ static bool do_f8dp4(DisasContext *s, gen_helper_gvec_3_ptr *fn,
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TRANS(FDOT_sb, do_f8dp4, gen_helper_gvec_fdot_sb, a->rd, a->rn, a->rm, 0)
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TRANS(FDOT_idx_sb, do_f8dp4, gen_helper_gvec_fdot_idx_sb,
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a->rd, a->rn, a->rm, a->index)
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+
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+static bool do_f8dp2(DisasContext *s, gen_helper_gvec_3_ptr *fn,
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+ int rd, int rn, int rm, int index)
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+{
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+ bool fp8dp2 = dc_isar_feature(aa64_f8dp2, s);
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+ bool ssve_fp8dp2 = dc_isar_feature(aa64_ssve_f8dp2, s);
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+ bool ok = false;
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+
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+ /* Feature detection and enabling are complex here. */
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+ if (!(ssve_fp8dp2 || (fp8dp2 && dc_isar_feature(aa64_sve2, s)))) {
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+ return false;
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+ }
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+ if (fpmr_access_check(s)) {
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+ if (fp8dp2) {
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+ s->is_nonstreaming = !ssve_fp8dp2;
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+ ok = sve_access_check(s);
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+ } else {
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+ ok = sme_sm_enabled_check(s);
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+ }
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+ }
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+
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+ if (ok) {
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+ unsigned vsz = vec_full_reg_size(s);
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+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
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+ vec_full_reg_offset(s, rn),
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+ vec_full_reg_offset(s, rm),
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+ tcg_env, vsz, vsz,
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+ index, fn);
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+ }
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+ return true;
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+}
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+
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+TRANS(FDOT_hb, do_f8dp2, gen_helper_gvec_fdot_hb, a->rd, a->rn, a->rm, 0)
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+TRANS(FDOT_idx_hb, do_f8dp2, gen_helper_gvec_fdot_idx_hb,
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+ a->rd, a->rn, a->rm, a->index)