target/riscv: Fix size of sw_check_code
The field only holds values of 2 and 3, fix its size to 8 bits and update stores from TCG. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-12-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
0c07391a14ac4cb5afeb9f3bc7b9d8665bf8151e
4 files changed
+9
-9
target/riscv/cpu.h
+1
-1
@@ -261,7 +261,7 @@ struct CPUArchState {
261
/* env place holder for extra word 2 during unwind */
262
uint64_t excp_uw2;
263
/* sw check code for sw check exception */
264
- target_ulong sw_check_code;
264
+ uint8_t sw_check_code;
265
#ifdef CONFIG_USER_ONLY
266
uint32_t elf_flags;
267
#endif
target/riscv/insn_trans/trans_rvi.c.inc
+4
-4
@@ -53,8 +53,8 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a)
53
/*
54
* misaligned, according to spec we should raise sw check exception
55
*/
56
- tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL),
57
- tcg_env, offsetof(CPURISCVState, sw_check_code));
56
+ tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL),
57
+ tcg_env, offsetof(CPURISCVState, sw_check_code));
58
gen_helper_raise_exception(tcg_env,
59
tcg_constant_i32(RISCV_EXCP_SW_CHECK));
60
return true;
@@ -66,8 +66,8 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a)
66
TCGv tmp = tcg_temp_new();
67
tcg_gen_extract_tl(tmp, get_gpr(ctx, xT2, EXT_NONE), 12, 20);
68
tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->label, skip);
69
- tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL),
70
- tcg_env, offsetof(CPURISCVState, sw_check_code));
69
+ tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL),
70
+ tcg_env, offsetof(CPURISCVState, sw_check_code));
71
gen_helper_raise_exception(tcg_env,
72
tcg_constant_i32(RISCV_EXCP_SW_CHECK));
73
gen_set_label(skip);
target/riscv/insn_trans/trans_rvzicfiss.c.inc
+2
-2
@@ -40,8 +40,8 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)
40
mxl_memop(ctx) | MO_ALIGN);
41
TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
42
tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip);
43
- tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_BCFI_TVAL),
44
- tcg_env, offsetof(CPURISCVState, sw_check_code));
43
+ tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_BCFI_TVAL),
44
+ tcg_env, offsetof(CPURISCVState, sw_check_code));
45
gen_update_pc(ctx, 0);
46
gen_helper_raise_exception(tcg_env,
47
tcg_constant_i32(RISCV_EXCP_SW_CHECK));
target/riscv/translate.c
+2
-2
@@ -1400,8 +1400,8 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
1400
if (ctx->fcfi_lp_expected) {
1401
/* Emit after insn_start, i.e. before the op following insn_start. */
1402
tcg_ctx->emit_before_op = QTAILQ_NEXT(ctx->base.insn_start, link);
1403
- tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL),
1404
- tcg_env, offsetof(CPURISCVState, sw_check_code));
1403
+ tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL),
1404
+ tcg_env, offsetof(CPURISCVState, sw_check_code));
1405
gen_helper_raise_exception(tcg_env,
1406
tcg_constant_i32(RISCV_EXCP_SW_CHECK));
1407
tcg_ctx->emit_before_op = NULL;