hw/arm/tegra241-cmdqv: Emulate VCMDQ register reads
Tegra241 CMDQV exposes per-VCMDQ register windows through two MMIO apertures: Direct VCMDQ aperture (0x10000/0x20000): VCMDQ Page0/Page1 VINTF logical aperture (0x30000/0x40000): VINTF0 LVCMDQ Page0/Page1 Both apertures are hardware aliases of the same underlying registers: Page 0 (control/status): CONS_INDX, PROD_INDX, CONFIG, STATUS, GERROR, GERRORN Page 1 (base/DRAM): BASE_L/H, CONS_INDX_BASE_DRAM_L/H The direct aperture Page 0 is programmable at any time so long as CMDQV_EN is enabled. The VINTF (logical) aperture Page 0 is programmable only once SW has mapped a VCMDQ to a VINTF; the "logical" view is local to that VINTF. Add read emulation for both apertures, backed by a single per-VCMDQ register cache. VINTF aperture reads are translated to their equivalent direct-aperture offset and served from the same cached state. Per the CMDQV architecture, a VCMDQ must be allocated to a Virtual Interface before it is used to send commands to the SMMU. Until that allocation happens, reads return cached register state with no HW interaction. Subsequent patches wire up IOMMU_HW_QUEUE_ALLOC, mmap the host VINTF Page 0, and install it into guest MMIO; after that, Page 0 reads from either aperture are served from the hardware-backed mmap'd page instead of the cache. Page 1 is also a hardware alias, but the kernel only exposes mmap for Page 0, so Page 1 reads always trap to QEMU and are served from cache. Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Message-id: 20260609112552.378999-17-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum <skolothumtho@nvidia.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Nicolin Chen committed
Jun 9, 2026 at 12:25 UTC
0d06b1cc2050fb8efdb9f023344b2e55125003f0
3 files changed
+321
hw/arm/tegra241-cmdqv.c
+103
@@ -16,6 +16,79 @@
16
#include "tegra241-cmdqv.h"
17
#include "trace.h"
18
19
+/*
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+ * Read a VCMDQ Page 0 register (control/status) using VCMDQ0_* offsets.
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+ *
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+ * The caller normalizes the MMIO offset such that @offset0 always refers
23
+ * to a VCMDQ0_* register, while @index selects the VCMDQ instance.
24
+ */
25
+static uint64_t tegra241_cmdqv_read_vcmdq_page0(Tegra241CMDQV *cmdqv,
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+ hwaddr offset0, int index,
27
+ bool direct)
28
+{
29
+ uint64_t val = 0;
30
+
31
+ switch (offset0) {
32
+ case A_VCMDQ0_CONS_INDX:
33
+ val = cmdqv->vcmdq_cons_indx[index];
34
+ break;
35
+ case A_VCMDQ0_PROD_INDX:
36
+ val = cmdqv->vcmdq_prod_indx[index];
37
+ break;
38
+ case A_VCMDQ0_CONFIG:
39
+ val = cmdqv->vcmdq_config[index];
40
+ break;
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+ case A_VCMDQ0_STATUS:
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+ val = cmdqv->vcmdq_status[index];
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+ break;
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+ case A_VCMDQ0_GERROR:
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+ val = cmdqv->vcmdq_gerror[index];
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+ break;
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+ case A_VCMDQ0_GERRORN:
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+ val = cmdqv->vcmdq_gerrorn[index];
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+ break;
50
+ default:
51
+ qemu_log_mask(LOG_UNIMP,
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+ "%s unhandled read access at 0x%" PRIx64 "\n",
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+ __func__, offset0);
54
+ }
55
+ trace_tegra241_cmdqv_read_vcmdq_page0(index, direct ? "direct" : "vi",
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+ offset0, val);
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+ return val;
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+}
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+
60
+/*
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+ * Read a VCMDQ Page 1 register (base / DRAM address) using VCMDQ0_* offsets.
62
+ */
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+static uint64_t tegra241_cmdqv_read_vcmdq_page1(Tegra241CMDQV *cmdqv,
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+ hwaddr offset0, int index,
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+ bool direct)
66
+{
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+ uint64_t val = 0;
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+
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+ switch (offset0) {
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+ case A_VCMDQ0_BASE_L:
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+ val = cmdqv->vcmdq_base[index];
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+ break;
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+ case A_VCMDQ0_BASE_H:
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+ val = cmdqv->vcmdq_base[index] >> 32;
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+ break;
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+ case A_VCMDQ0_CONS_INDX_BASE_DRAM_L:
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+ val = cmdqv->vcmdq_cons_indx_base[index];
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+ break;
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+ case A_VCMDQ0_CONS_INDX_BASE_DRAM_H:
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+ val = cmdqv->vcmdq_cons_indx_base[index] >> 32;
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+ break;
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+ default:
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+ qemu_log_mask(LOG_UNIMP,
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+ "%s unhandled read access at 0x%" PRIx64 "\n",
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+ __func__, offset0);
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+ }
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+ trace_tegra241_cmdqv_read_vcmdq_page1(index, direct ? "direct" : "vi",
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+ offset0, val);
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+ return val;
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+}
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+
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static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv,
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hwaddr offset)
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{
@@ -93,6 +166,7 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset,
166
{
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Tegra241CMDQV *cmdqv = (Tegra241CMDQV *)opaque;
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uint64_t val = 0;
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+ int index;
170
171
if (offset >= TEGRA241_CMDQV_IO_LEN) {
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qemu_log_mask(LOG_UNIMP,
@@ -126,6 +200,35 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset,
200
case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3:
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val = tegra241_cmdqv_config_vintf_read(cmdqv, offset);
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break;
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+ case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN:
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+ /*
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+ * VINTF Page0 registers are hardware aliases of VCMDQ Page0 registers.
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+ * Translate the VINTF aperture offset to its VCMDQ Page0 equivalent
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+ * before dispatching to the Page 0 helper.
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+ */
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+ offset -= CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE;
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+ index = (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE;
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+ return tegra241_cmdqv_read_vcmdq_page0(cmdqv,
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+ offset - index * CMDQV_VCMDQ_STRIDE, index, false);
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+ case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN:
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+ /*
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+ * Decode a per-VCMDQ Page 0 access. Each VCMDQ occupies a
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+ * CMDQV_VCMDQ_STRIDE-byte window; extract the index and normalize
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+ * to the VCMDQ0_* offset before calling the Page 0 helper.
218
+ */
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+ index = (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE;
220
+ return tegra241_cmdqv_read_vcmdq_page0(cmdqv,
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+ offset - index * CMDQV_VCMDQ_STRIDE, index, true);
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+ case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H:
223
+ /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above. */
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+ offset -= CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE;
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+ index = (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE;
226
+ return tegra241_cmdqv_read_vcmdq_page1(cmdqv,
227
+ offset - index * CMDQV_VCMDQ_STRIDE, index, false);
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+ case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H:
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+ index = (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE;
230
+ return tegra241_cmdqv_read_vcmdq_page1(cmdqv,
231
+ offset - index * CMDQV_VCMDQ_STRIDE, index, true);
232
default:
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qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 "\n",
234
__func__, offset);
hw/arm/tegra241-cmdqv.h
+216
@@ -30,6 +30,13 @@
30
*/
31
#define TEGRA241_CMDQV_IO_LEN 0x50000
32
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+/* CMDQV MMIO aperture bases and VCMDQ stride */
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+#define CMDQV_VCMDQ_PAGE0_BASE 0x10000 /* CMDQV_CMDQ_BASE */
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+#define CMDQV_VCMDQ_PAGE1_BASE 0x20000
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+#define CMDQV_VINTF_PAGE0_BASE 0x30000 /* CMDQV_VI_CMDQ_BASE */
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+#define CMDQV_VINTF_PAGE1_BASE 0x40000
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+#define CMDQV_VCMDQ_STRIDE 0x80
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+
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#define VINTF_PAGE_SIZE 0x10000
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42
struct iommu_viommu_tegra241_cmdqv;
@@ -57,6 +64,19 @@ typedef struct Tegra241CMDQV {
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uint32_t vintf_sid_match[TEGRA241_CMDQV_MAX_NUM_SID];
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uint32_t vintf_sid_replace[TEGRA241_CMDQV_MAX_NUM_SID];
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uint32_t vintf_cmdq_err_map[4];
67
+ /*
68
+ * VCMDQ register cache. The direct (VCMDQ aperture) and logical
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+ * (VINTF aperture) views are hardware aliases; both are served from
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+ * this single cached copy.
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+ */
72
+ uint32_t vcmdq_cons_indx[TEGRA241_CMDQV_MAX_CMDQ];
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+ uint32_t vcmdq_prod_indx[TEGRA241_CMDQV_MAX_CMDQ];
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+ uint32_t vcmdq_config[TEGRA241_CMDQV_MAX_CMDQ];
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+ uint32_t vcmdq_status[TEGRA241_CMDQV_MAX_CMDQ];
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+ uint32_t vcmdq_gerror[TEGRA241_CMDQV_MAX_CMDQ];
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+ uint32_t vcmdq_gerrorn[TEGRA241_CMDQV_MAX_CMDQ];
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+ uint64_t vcmdq_base[TEGRA241_CMDQV_MAX_CMDQ];
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+ uint64_t vcmdq_cons_indx_base[TEGRA241_CMDQV_MAX_CMDQ];
80
} Tegra241CMDQV;
81
82
/* CMDQ-V Config page registers (offset 0x00000) */
@@ -148,6 +168,202 @@ REG32(VINTF0_LVCMDQ_ERR_MAP_0, 0x10c0)
168
FIELD(VINTF0_LVCMDQ_ERR_MAP_0, LVCMDQ_ERR_MAP, 0, 32)
169
#define A_VINTF0_LVCMDQ_ERR_MAP_3 (A_VINTF0_LVCMDQ_ERR_MAP_0 + 3 * 4)
170
171
+/*
172
+ * Direct VCMDQ aperture register windows.
173
+ *
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+ * Page 0 @ CMDQV_VCMDQ_PAGE0_BASE: VCMDQ control and status registers.
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+ * Page 1 @ CMDQV_VCMDQ_PAGE1_BASE: VCMDQ base and DRAM address registers.
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+ *
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+ * Each VCMDQ occupies a CMDQV_VCMDQ_STRIDE-byte slot within its page.
178
+ */
179
+
180
+/* --- Page 0 register macros --- */
181
+#define SMMU_CMDQV_VCMDQi_CONS_INDX_(i) \
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+ REG32(VCMDQ##i##_CONS_INDX, \
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+ CMDQV_VCMDQ_PAGE0_BASE + i * CMDQV_VCMDQ_STRIDE) \
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+ FIELD(VCMDQ##i##_CONS_INDX, RD, 0, 20) \
185
+ FIELD(VCMDQ##i##_CONS_INDX, ERR, 24, 7)
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+
187
+#define V_VCMDQ_CONS_INDX_ERR_CERROR_NONE 0
188
+#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_OPCODE 1
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+#define V_VCMDQ_CONS_INDX_ERR_CERROR_ABT 2
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+#define V_VCMDQ_CONS_INDX_ERR_CERROR_ATC_INV_SYNC 3
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+#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_ACCESS 4
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+
193
+#define SMMU_CMDQV_VCMDQi_PROD_INDX_(i) \
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+ REG32(VCMDQ##i##_PROD_INDX, \
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+ CMDQV_VCMDQ_PAGE0_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \
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+ FIELD(VCMDQ##i##_PROD_INDX, WR, 0, 20)
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+
198
+#define SMMU_CMDQV_VCMDQi_CONFIG_(i) \
199
+ REG32(VCMDQ##i##_CONFIG, \
200
+ CMDQV_VCMDQ_PAGE0_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \
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+ FIELD(VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1)
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+
203
+#define SMMU_CMDQV_VCMDQi_STATUS_(i) \
204
+ REG32(VCMDQ##i##_STATUS, \
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+ CMDQV_VCMDQ_PAGE0_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \
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+ FIELD(VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1)
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+
208
+#define SMMU_CMDQV_VCMDQi_GERROR_(i) \
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+ REG32(VCMDQ##i##_GERROR, \
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+ CMDQV_VCMDQ_PAGE0_BASE + 0x10 + i * CMDQV_VCMDQ_STRIDE) \
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+ FIELD(VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \
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+ FIELD(VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \
213
+ FIELD(VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1)
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+
215
+#define SMMU_CMDQV_VCMDQi_GERRORN_(i) \
216
+ REG32(VCMDQ##i##_GERRORN, \
217
+ CMDQV_VCMDQ_PAGE0_BASE + 0x14 + i * CMDQV_VCMDQ_STRIDE) \
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+ FIELD(VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \
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+ FIELD(VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \
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+ FIELD(VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1)
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+
222
+/* Page 0 layout: VCMDQ0 */
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+SMMU_CMDQV_VCMDQi_CONS_INDX_(0)
224
+SMMU_CMDQV_VCMDQi_PROD_INDX_(0)
225
+SMMU_CMDQV_VCMDQi_CONFIG_(0)
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+SMMU_CMDQV_VCMDQi_STATUS_(0)
227
+SMMU_CMDQV_VCMDQi_GERROR_(0)
228
+SMMU_CMDQV_VCMDQi_GERRORN_(0)
229
+
230
+/* Page 0 layout: VCMDQ1 */
231
+SMMU_CMDQV_VCMDQi_CONS_INDX_(1)
232
+SMMU_CMDQV_VCMDQi_PROD_INDX_(1)
233
+SMMU_CMDQV_VCMDQi_CONFIG_(1)
234
+SMMU_CMDQV_VCMDQi_STATUS_(1)
235
+SMMU_CMDQV_VCMDQi_GERROR_(1)
236
+SMMU_CMDQV_VCMDQi_GERRORN_(1)
237
+
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+/* --- Page 1 register macros --- */
239
+#define SMMU_CMDQV_VCMDQi_BASE_L_(i) \
240
+ REG32(VCMDQ##i##_BASE_L, CMDQV_VCMDQ_PAGE1_BASE + i * CMDQV_VCMDQ_STRIDE) \
241
+ FIELD(VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \
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+ FIELD(VCMDQ##i##_BASE_L, ADDR, 5, 27)
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+
244
+#define SMMU_CMDQV_VCMDQi_BASE_H_(i) \
245
+ REG32(VCMDQ##i##_BASE_H, \
246
+ CMDQV_VCMDQ_PAGE1_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \
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+ FIELD(VCMDQ##i##_BASE_H, ADDR, 0, 16)
248
+
249
+#define SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(i) \
250
+ REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, \
251
+ CMDQV_VCMDQ_PAGE1_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \
252
+ FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32)
253
+
254
+#define SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(i) \
255
+ REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, \
256
+ CMDQV_VCMDQ_PAGE1_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \
257
+ FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16)
258
+
259
+/* Page 1 layout: VCMDQ0 */
260
+SMMU_CMDQV_VCMDQi_BASE_L_(0)
261
+SMMU_CMDQV_VCMDQi_BASE_H_(0)
262
+SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(0)
263
+SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(0)
264
+
265
+/* Page 1 layout: VCMDQ1 */
266
+SMMU_CMDQV_VCMDQi_BASE_L_(1)
267
+SMMU_CMDQV_VCMDQi_BASE_H_(1)
268
+SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(1)
269
+SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(1)
270
+
271
+/*
272
+ * VINTF0 logical VCMDQ aperture register windows.
273
+ *
274
+ * Page 0 @ CMDQV_VINTF_PAGE0_BASE: VCMDQ control and status registers.
275
+ * Page 1 @ CMDQV_VINTF_PAGE1_BASE: VCMDQ base and DRAM address registers.
276
+ *
277
+ * VCMDQs mapped via VINTF are accessed through this aperture as
278
+ * hardware aliases of the direct VCMDQ aperture above.
279
+ */
280
+
281
+/* --- Page 0 register macros --- */
282
+#define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(i) \
283
+ REG32(VI_VCMDQ##i##_CONS_INDX, \
284
+ CMDQV_VINTF_PAGE0_BASE + i * CMDQV_VCMDQ_STRIDE) \
285
+ FIELD(VI_VCMDQ##i##_CONS_INDX, RD, 0, 20) \
286
+ FIELD(VI_VCMDQ##i##_CONS_INDX, ERR, 24, 7)
287
+
288
+#define SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(i) \
289
+ REG32(VI_VCMDQ##i##_PROD_INDX, \
290
+ CMDQV_VINTF_PAGE0_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \
291
+ FIELD(VI_VCMDQ##i##_PROD_INDX, WR, 0, 20)
292
+
293
+#define SMMU_CMDQV_VI_VCMDQi_CONFIG_(i) \
294
+ REG32(VI_VCMDQ##i##_CONFIG, \
295
+ CMDQV_VINTF_PAGE0_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \
296
+ FIELD(VI_VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1)
297
+
298
+#define SMMU_CMDQV_VI_VCMDQi_STATUS_(i) \
299
+ REG32(VI_VCMDQ##i##_STATUS, \
300
+ CMDQV_VINTF_PAGE0_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \
301
+ FIELD(VI_VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1)
302
+
303
+#define SMMU_CMDQV_VI_VCMDQi_GERROR_(i) \
304
+ REG32(VI_VCMDQ##i##_GERROR, \
305
+ CMDQV_VINTF_PAGE0_BASE + 0x10 + i * CMDQV_VCMDQ_STRIDE) \
306
+ FIELD(VI_VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \
307
+ FIELD(VI_VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \
308
+ FIELD(VI_VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1)
309
+
310
+#define SMMU_CMDQV_VI_VCMDQi_GERRORN_(i) \
311
+ REG32(VI_VCMDQ##i##_GERRORN, \
312
+ CMDQV_VINTF_PAGE0_BASE + 0x14 + i * CMDQV_VCMDQ_STRIDE) \
313
+ FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \
314
+ FIELD(VI_VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \
315
+ FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1)
316
+
317
+/* Page 0 layout: VCMDQ0 */
318
+SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(0)
319
+SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(0)
320
+SMMU_CMDQV_VI_VCMDQi_CONFIG_(0)
321
+SMMU_CMDQV_VI_VCMDQi_STATUS_(0)
322
+SMMU_CMDQV_VI_VCMDQi_GERROR_(0)
323
+SMMU_CMDQV_VI_VCMDQi_GERRORN_(0)
324
+
325
+/* Page 0 layout: VCMDQ1 */
326
+SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(1)
327
+SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(1)
328
+SMMU_CMDQV_VI_VCMDQi_CONFIG_(1)
329
+SMMU_CMDQV_VI_VCMDQi_STATUS_(1)
330
+SMMU_CMDQV_VI_VCMDQi_GERROR_(1)
331
+SMMU_CMDQV_VI_VCMDQi_GERRORN_(1)
332
+
333
+/* --- Page 1 register macros --- */
334
+#define SMMU_CMDQV_VI_VCMDQi_BASE_L_(i) \
335
+ REG32(VI_VCMDQ##i##_BASE_L, \
336
+ CMDQV_VINTF_PAGE1_BASE + i * CMDQV_VCMDQ_STRIDE) \
337
+ FIELD(VI_VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \
338
+ FIELD(VI_VCMDQ##i##_BASE_L, ADDR, 5, 27)
339
+
340
+#define SMMU_CMDQV_VI_VCMDQi_BASE_H_(i) \
341
+ REG32(VI_VCMDQ##i##_BASE_H, \
342
+ CMDQV_VINTF_PAGE1_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \
343
+ FIELD(VI_VCMDQ##i##_BASE_H, ADDR, 0, 16)
344
+
345
+#define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(i) \
346
+ REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, \
347
+ CMDQV_VINTF_PAGE1_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \
348
+ FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32)
349
+
350
+#define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(i) \
351
+ REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, \
352
+ CMDQV_VINTF_PAGE1_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \
353
+ FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16)
354
+
355
+/* Page 1 layout: VCMDQ0 */
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+SMMU_CMDQV_VI_VCMDQi_BASE_L_(0)
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+SMMU_CMDQV_VI_VCMDQi_BASE_H_(0)
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+SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(0)
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+SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(0)
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+
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+/* Page 1 layout: VCMDQ1 */
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+SMMU_CMDQV_VI_VCMDQi_BASE_L_(1)
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+SMMU_CMDQV_VI_VCMDQi_BASE_H_(1)
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+SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(1)
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+SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(1)
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+
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const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);
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#endif /* HW_ARM_TEGRA241_CMDQV_H */
hw/arm/trace-events
+2
@@ -75,6 +75,8 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_id) "vS
75
# tegra241-cmdqv
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tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "offset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x"
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tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "offset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x"
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+tegra241_cmdqv_read_vcmdq_page0(int index, const char *aperture, uint64_t offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64
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+tegra241_cmdqv_read_vcmdq_page1(int index, const char *aperture, uint64_t offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64
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# strongarm.c
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strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d"