target/arm/tcg: increase cache level for cpu=max
This patch addresses cache description in the `aarch64_max_tcg_initfn` function for cpu=max. It introduces three levels of caches and modifies the cache description registers accordingly. Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Message-id: 20260311160609.358-2-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alireza Sanaee committed
Apr 23, 2026 at 10:24 UTC
0dc85587be2edc7cdeaeebed4723b53c68a7e57d
1 file changed
+10
target/arm/tcg/cpu64.c
+10
@@ -1167,6 +1167,16 @@ void aarch64_max_tcg_initfn(Object *obj)
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uint64_t t;
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uint32_t u;
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+ SET_IDREG(isar, CLIDR, 0x8200123);
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+ /* 64KB L1 dcache */
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+ cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
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+ /* 64KB L1 icache */
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+ cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
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+ /* 1MB L2 unified cache */
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+ cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7);
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+ /* 2MB L3 unified cache */
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+ cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7);
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+
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/*
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* Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
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* to because we started with aarch64_a57_initfn(). A 'max' CPU might