target/riscv: Fix size of excp_uw2
Fix to 64 bits to match size of instruction start words. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-11-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
0ddb30db188247e84abb8aca85081ec5769ac09e
2 files changed
+2
-2
target/riscv/cpu.h
+1
-1
@@ -259,7 +259,7 @@ struct CPUArchState {
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/* shadow stack register for zicfiss extension */
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uint64_t ssp;
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/* env place holder for extra word 2 during unwind */
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- target_ulong excp_uw2;
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+ uint64_t excp_uw2;
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/* sw check code for sw check exception */
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target_ulong sw_check_code;
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#ifdef CONFIG_USER_ONLY
target/riscv/translate.c
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-1
@@ -231,7 +231,7 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
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tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
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}
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-static void decode_save_opc(DisasContext *ctx, target_ulong excp_uw2)
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+static void decode_save_opc(DisasContext *ctx, uint64_t excp_uw2)
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{
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assert(!ctx->insn_start_updated);
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ctx->insn_start_updated = true;