@samitouri / QOSamiQemu / commits / 0df0769365

target/riscv: Add big-endian CPU configuration field and reset logic

Add a big_endian field to RISCVCPUConfig and wire it into the CPU reset path. When cfg.big_endian is set, riscv_cpu_reset_hold() writes 1 into the MSTATUS MBE/SBE/UBE fields using set_field(); otherwise it writes 0. This makes the reset value deterministic on both cold and warm reset. This models fixed-endian harts, not mixed-endian implementations where the guest can toggle MBE/SBE/UBE at runtime. The MBE/SBE/UBE bits are not included in the writable mask of any mstatus/mstatush/sstatus CSR write path (unchanged by this series), so the value chosen at reset is effectively hardwired per section 3.1.6.5 of the RISC-V Privileged Specification. The user-facing property and documentation are added in a later patch, once the full endianness support is in place. Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Message-ID: <20260527201348.29511-10-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Djordje Todorovic committed May 27, 2026 at 22:13 UTC 0df0769365cca0d9e1f10f3bc4f4d43c6a18d5c8

2 files changed +8

target/riscv/cpu.c

@@ -740,6 +740,13 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)

740 env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1);

741 }

742 }

743 + /*

744 + * Model fixed-endian harts: MBE/SBE/UBE are initialized from the

745 + * CPU configuration and are intentionally not writable via status CSRs.

746 + */

747 + env->mstatus = set_field(env->mstatus, MSTATUS_MBE, cpu->cfg.big_endian);

748 + env->mstatus = set_field(env->mstatus, MSTATUS_SBE, cpu->cfg.big_endian);

749 + env->mstatus = set_field(env->mstatus, MSTATUS_UBE, cpu->cfg.big_endian);

750 env->mcause = 0;

751 env->miclaim = MIP_SGEIP;

752 env->pc = env->resetvec;

target/riscv/cpu_cfg_fields.h.inc

@@ -157,6 +157,7 @@ BOOL_FIELD(ext_xmipscmov)

157 BOOL_FIELD(ext_xmipslsp)

158 BOOL_FIELD(ext_xlrbr)

159

160 +BOOL_FIELD(big_endian)

161 BOOL_FIELD(mmu)

162 BOOL_FIELD(pmp)

163 BOOL_FIELD(debug)