target/arm: Implement FMLALL{BB, BT, TB, TT} for AdvSIMD
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
0e81c215da2f69c13603b3d13cf6884fcd2246c2
4 files changed
+68
target/arm/tcg/a64.decode
+7
@@ -1220,6 +1220,10 @@ FCVTN_bs 0.00 1110 000 ..... 11110 1 ..... ..... @qrrr_h
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FMLAL_hb_v 0 idxn:1 00 1110 110 rm:5 11111 1 rn:5 rd:5 \
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&rxx idxm=0
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+%fmlall_idxn 30:1 22:1
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+FMLALL_sb_v 0.00 1110 0.0 rm:5 110001 rn:5 rd:5 \
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+ &rxx idxm=0 idxn=%fmlall_idxn
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+
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### Advanced SIMD scalar x indexed element
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FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
@@ -1341,6 +1345,9 @@ SQDMLSL_vi 0.00 1111 10 . ..... 0111 . 0 ..... ..... @qrrx_s
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FMLAL_hb_vi 0 idxn:1 00 1111 11 ... rm:3 0000 . 0 rn:5 rd:5 \
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&rxx idxm=%hlm4
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+FMLALL_sb_vi 0 . 10 1111 0 . ... rm:3 1000 . 0 rn:5 rd:5 \
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+ &rxx idxm=%hlm4 idxn=%fmlall_idxn
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+
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# Floating-point conditional select
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FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd
target/arm/tcg/fp8_helper.c
+55
@@ -630,6 +630,16 @@ static float16 f8dotadd_h(uint64_t a, uint64_t b, int n, float16 c,
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return float16_round_pack_canonical(&p0, &ctx->stat);
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}
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+static float32 f8dotadd_s(uint64_t a, uint64_t b, int n, float32 c,
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+ FP8MulContext *ctx)
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+{
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+ FloatParts64 p0 = f8dot(a, b, n, ctx);
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+ FloatParts64 p1 = float32_unpack_canonical(c, &ctx->stat);
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+
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+ p0 = parts64_addsub(&p0, &p1, &ctx->stat, false);
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+ return float32_round_pack_canonical(&p0, &ctx->stat);
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+}
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+
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void HELPER(gvec_fmla_hb)(void *vd, void *vn, void *vm,
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CPUARMState *env, uint32_t desc)
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{
@@ -674,3 +684,48 @@ void HELPER(gvec_fmla_idx_hb)(void *vd, void *vn, void *vm,
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clear_tail(vd, oprsz, simd_maxsz(desc));
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}
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+
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+void HELPER(gvec_fmla_sb)(void *vd, void *vn, void *vm,
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+ CPUARMState *env, uint32_t desc)
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+{
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+ FP8MulContext ctx = fp8_mul_start(env, -1);
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+ size_t idx = extract32(desc, SIMD_DATA_SHIFT, 2);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 4;
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+ uint8_t *n = vn;
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+ uint8_t *m = vm;
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+ float32 *d = vd;
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+
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+ for (size_t i = 0; i < nelem; i++) {
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+ uint8_t e0 = n[H1(4 * i + idx)];
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+ uint8_t e1 = m[H1(4 * i + idx)];
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+
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+ d[H4(i)] = f8dotadd_s(e0, e1, 1, d[H4(i)], &ctx);
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+ }
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+
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+ clear_tail(vd, oprsz, simd_maxsz(desc));
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+}
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+
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+void HELPER(gvec_fmla_idx_sb)(void *vd, void *vn, void *vm,
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+ CPUARMState *env, uint32_t desc)
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+{
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+ FP8MulContext ctx = fp8_mul_start(env, -1);
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+ size_t idx_n = extract32(desc, SIMD_DATA_SHIFT, 2);
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+ size_t idx_m = extract32(desc, SIMD_DATA_SHIFT + 2, 4);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 4;
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+ uint8_t *n = vn;
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+ uint8_t *m = vm;
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+ float32 *d = vd;
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+ size_t i = 0;
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+
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+ do {
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+ uint8_t e1 = m[4 * i + H1(idx_m)];
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+ do {
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+ uint8_t e0 = n[H1(4 * i + idx_n)];
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+ d[H4(i)] = f8dotadd_s(e0, e1, 1, d[H4(i)], &ctx);
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+ } while (++i % 4 != 0);
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+ } while (i < nelem);
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+
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+ clear_tail(vd, oprsz, simd_maxsz(desc));
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+}
target/arm/tcg/helper-fp8-defs.h
+3
@@ -26,3 +26,6 @@ DEF_HELPER_FLAGS_4(sme2_fcvtn_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_5(gvec_fmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_5(gvec_fmla_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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+
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+DEF_HELPER_FLAGS_5(gvec_fmla_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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+DEF_HELPER_FLAGS_5(gvec_fmla_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
target/arm/tcg/translate-a64.c
+3
@@ -7497,6 +7497,9 @@ static bool do_fmla_fp8(DisasContext *s, arg_rxx *a,
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TRANS_FEAT(FMLAL_hb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)
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TRANS_FEAT(FMLAL_hb_vi, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)
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+TRANS_FEAT(FMLALL_sb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_sb)
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+TRANS_FEAT(FMLALL_sb_vi, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_sb)
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+
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static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,
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gen_helper_gvec_3 * const fns[2])
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{