linux-user/riscv: write the floating-point registers to a core dump
Write an NT_FPREGSET note for RISC-V, matching struct __riscv_d_ext_state from uapi/asm/ptrace.h: f0-f31 as 64-bit values followed by fcsr. Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Helge Deller <deller@gmx.de>
Matt Turner committed
Aug 5, 2026 at 13:15 UTC
0f183237d24daac28b6290b0605cba7b47aa8052
2 files changed
+20
linux-user/riscv/elfload.c
+9
@@ -11,6 +11,15 @@ const char *get_elf_cpu_model(uint32_t eflags)
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return "max";
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}
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+void elf_core_copy_fpregs(target_elf_fpregset_t *r, const CPURISCVState *env)
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+{
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+ for (int i = 0; i < 32; i++) {
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+ r->fpr[i] = tswap64(env->fpr[i]);
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+ }
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+ r->fcsr = tswap32(((uint32_t)env->frm << FSR_RD_SHIFT) |
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+ (riscv_cpu_get_fflags((CPURISCVState *)env) << FSR_AEXC_SHIFT));
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+}
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+
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void elf_core_copy_regs(target_elf_gregset_t *r, const CPURISCVState *env)
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{
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r->pc = tswapal(env->pc);
linux-user/riscv/target_elf.h
+11
@@ -27,4 +27,15 @@ typedef struct target_elf_gregset_t {
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abi_ulong regs[31];
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} target_elf_gregset_t;
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+#define HAVE_ELF_CORE_FPREGS 1
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+
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+/*
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+ * Matches struct __riscv_d_ext_state from uapi/asm/ptrace.h:
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+ * f0-f31 as 64-bit values followed by fcsr.
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+ */
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+typedef struct target_elf_fpregset_t {
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+ uint64_t fpr[32];
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+ uint32_t fcsr;
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+} target_elf_fpregset_t;
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+
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#endif