target/ppc: convert sraw[i] instruction via decode spec
Move sraw and srawi to decodetree specification using the @X_rc format. The existing shift-masking logic from gen_sraw/gen_srawi is preserved verbatim in the new trans_SRAW/trans_SRAWI handlers. Signed-off-by: Mukesh Kumar Chaurasiya (IBM) <mkchauras@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-9-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Mukesh Kumar Chaurasiya (IBM) committed
Aug 27, 2026 at 18:59 UTC
0f1feac37ba7d2180693bcd076e881315531d2e4
5 files changed
+45
-44
target/ppc/helper.h
+1
-1
@@ -64,7 +64,7 @@ DEF_HELPER_4(DIVWE, tl, env, tl, tl, i32)
64
65
DEF_HELPER_FLAGS_1(POPCNTB, TCG_CALL_NO_RWG_SE, tl, tl)
66
DEF_HELPER_FLAGS_2(CMPB, TCG_CALL_NO_RWG_SE, tl, tl, tl)
67
-DEF_HELPER_3(sraw, tl, env, tl, tl)
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+DEF_HELPER_3(SRAW, tl, env, tl, tl)
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DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
70
DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
target/ppc/insn32.decode
+2
@@ -509,6 +509,8 @@ HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW
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510
SLW 011111 ..... ..... ..... 0000011000 . @X_rc
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SRW 011111 ..... ..... ..... 1000011000 . @X_rc
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+SRAW 011111 ..... ..... ..... 1100011000 . @X_rc
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+SRAWI 011111 ..... ..... ..... 1100111000 . @X_rc
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515
## BCD Assist
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target/ppc/int_helper.c
+1
-1
@@ -235,7 +235,7 @@ target_ulong helper_CMPB(target_ulong rs, target_ulong rb)
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}
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/* shift right arithmetic helper */
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-target_ulong helper_sraw(CPUPPCState *env, target_ulong value,
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+target_ulong helper_SRAW(CPUPPCState *env, target_ulong value,
239
target_ulong shift)
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{
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int32_t ret;
target/ppc/translate.c
-42
@@ -2316,46 +2316,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2316
/*** Integer shift ***/
2317
2318
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-/* sraw & sraw. */
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-static void gen_sraw(DisasContext *ctx)
2321
-{
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- gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env,
2323
- cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2324
- if (unlikely(Rc(ctx->opcode) != 0)) {
2325
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2326
- }
2327
-}
2328
-
2329
-/* srawi & srawi. */
2330
-static void gen_srawi(DisasContext *ctx)
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-{
2332
- int sh = SH(ctx->opcode);
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- TCGv dst = cpu_gpr[rA(ctx->opcode)];
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- TCGv src = cpu_gpr[rS(ctx->opcode)];
2335
- if (sh == 0) {
2336
- tcg_gen_ext32s_tl(dst, src);
2337
- tcg_gen_movi_tl(cpu_ca, 0);
2338
- if (is_isa300(ctx)) {
2339
- tcg_gen_movi_tl(cpu_ca32, 0);
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- }
2341
- } else {
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- TCGv t0;
2343
- tcg_gen_ext32s_tl(dst, src);
2344
- tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2345
- t0 = tcg_temp_new();
2346
- tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2347
- tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2348
- tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2349
- if (is_isa300(ctx)) {
2350
- tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2351
- }
2352
- tcg_gen_sari_tl(dst, dst, sh);
2353
- }
2354
- if (unlikely(Rc(ctx->opcode) != 0)) {
2355
- gen_set_Rc0(ctx, dst);
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- }
2357
-}
2358
-
2319
#if defined(TARGET_PPC64)
2320
/* sld & sld. */
2321
static void gen_sld(DisasContext *ctx)
@@ -5717,8 +5677,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
5677
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
5720
-GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
5721
-GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
5680
#if defined(TARGET_PPC64)
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GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
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GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
target/ppc/translate/fixedpoint-impl.c.inc
+41
@@ -1454,3 +1454,44 @@ static bool trans_SRW(DisasContext *ctx, arg_SRW *a)
1454
}
1455
return true;
1456
}
1457
+
1458
+/* sraw & sraw. */
1459
+static bool trans_SRAW(DisasContext *ctx, arg_SRAW *a)
1460
+{
1461
+ gen_helper_SRAW(cpu_gpr[a->ra], tcg_env,
1462
+ cpu_gpr[a->rt], cpu_gpr[a->rb]);
1463
+ if (unlikely(a->rc)) {
1464
+ gen_set_Rc0(ctx, cpu_gpr[a->ra]);
1465
+ }
1466
+ return true;
1467
+}
1468
+
1469
+/* srawi & srawi. */
1470
+static bool trans_SRAWI(DisasContext *ctx, arg_SRAWI *a)
1471
+{
1472
+ TCGv dst = cpu_gpr[a->ra];
1473
+ TCGv src = cpu_gpr[a->rt];
1474
+ if (a->rb == 0) {
1475
+ tcg_gen_ext32s_tl(dst, src);
1476
+ tcg_gen_movi_tl(cpu_ca, 0);
1477
+ if (is_isa300(ctx)) {
1478
+ tcg_gen_movi_tl(cpu_ca32, 0);
1479
+ }
1480
+ } else {
1481
+ TCGv t0;
1482
+ tcg_gen_ext32s_tl(dst, src);
1483
+ tcg_gen_andi_tl(cpu_ca, dst, (1ULL << a->rb) - 1);
1484
+ t0 = tcg_temp_new();
1485
+ tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1486
+ tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1487
+ tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1488
+ if (is_isa300(ctx)) {
1489
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1490
+ }
1491
+ tcg_gen_sari_tl(dst, dst, a->rb);
1492
+ }
1493
+ if (unlikely(a->rc)) {
1494
+ gen_set_Rc0(ctx, dst);
1495
+ }
1496
+ return true;
1497
+}