target/arm: Implement FDOT (FP8 to FP16) for AdvSIMD
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-38-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:21 UTC
0f668e0aee650b76eb429f9d49c34b706cdc6486
5 files changed
+51
target/arm/cpu-features.h
+5
@@ -1635,6 +1635,11 @@ static inline bool isar_feature_aa64_f8dp4(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8DP4);
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}
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+static inline bool isar_feature_aa64_f8dp2(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8DP2);
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+}
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+
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/*
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* Combinations of feature tests, for ease of use with TRANS_FEAT.
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*/
target/arm/tcg/a64.decode
+2
@@ -1225,6 +1225,7 @@ FMLALL_sb_v 0.00 1110 0.0 rm:5 110001 rn:5 rd:5 \
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&rxx idxm=0 idxn=%fmlall_idxn
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FDOT_sb_v 0.00 1110 000 ..... 11111 1 ..... ..... @qrrr_s
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+FDOT_hb_v 0.00 1110 010 ..... 11111 1 ..... ..... @qrrr_h
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### Advanced SIMD scalar x indexed element
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@@ -1351,6 +1352,7 @@ FMLALL_sb_vi 0 . 10 1111 0 . ... rm:3 1000 . 0 rn:5 rd:5 \
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&rxx idxm=%hlm4 idxn=%fmlall_idxn
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FDOT_sb_vi 0.00 1111 00 . ..... 0000 . 0 ..... ..... @qrrx_s
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+FDOT_hb_vi 0.00 1111 01 .. .... 0000 . 0 ..... ..... @qrrx_h
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# Floating-point conditional select
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target/arm/tcg/fp8_helper.c
+39
@@ -768,3 +768,42 @@ void HELPER(gvec_fdot_idx_sb)(void *vd, void *vn, void *vm,
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clear_tail(vd, oprsz, simd_maxsz(desc));
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}
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+
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+void HELPER(gvec_fdot_hb)(void *vd, void *vn, void *vm,
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+ CPUARMState *env, uint32_t desc)
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+{
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+ FP8MulContext ctx = fp8_mul_start(env, 0xf);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 2;
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+ uint16_t *n = vn;
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+ uint16_t *m = vm;
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+ float16 *d = vd;
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+
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+ for (size_t i = 0; i < nelem; i++) {
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+ d[i] = f8dotadd_h(n[i], m[i], 2, d[i], &ctx);
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+ }
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+
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+ clear_tail(vd, oprsz, simd_maxsz(desc));
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+}
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+
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+void HELPER(gvec_fdot_idx_hb)(void *vd, void *vn, void *vm,
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+ CPUARMState *env, uint32_t desc)
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+{
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+ FP8MulContext ctx = fp8_mul_start(env, 0xf);
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+ size_t idx = simd_data(desc);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 2;
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+ uint16_t *n = vn;
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+ uint16_t *m = vm;
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+ float16 *d = vd;
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+ size_t i = 0;
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+
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+ do {
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+ uint16_t e1 = m[i + H2(idx)];
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+ do {
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+ d[i] = f8dotadd_h(n[i], e1, 2, d[i], &ctx);
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+ } while (++i % 8 != 0);
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+ } while (i < nelem);
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+
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+ clear_tail(vd, oprsz, simd_maxsz(desc));
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+}
target/arm/tcg/helper-fp8-defs.h
+3
@@ -32,3 +32,6 @@ DEF_HELPER_FLAGS_5(gvec_fmla_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
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DEF_HELPER_FLAGS_5(gvec_fdot_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_5(gvec_fdot_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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+
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+DEF_HELPER_FLAGS_5(gvec_fdot_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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+DEF_HELPER_FLAGS_5(gvec_fdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
target/arm/tcg/translate-a64.c
+2
@@ -7514,6 +7514,7 @@ static bool do_f8dot(DisasContext *s, arg_qrrr_e *a,
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}
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TRANS_FEAT(FDOT_sb_v, aa64_f8dp4, do_f8dot, a, gen_helper_gvec_fdot_sb)
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+TRANS_FEAT(FDOT_hb_v, aa64_f8dp2, do_f8dot, a, gen_helper_gvec_fdot_hb)
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static bool do_f8dot_idx(DisasContext *s, arg_qrrx_e *a,
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gen_helper_gvec_3_ptr *fn)
@@ -7529,6 +7530,7 @@ static bool do_f8dot_idx(DisasContext *s, arg_qrrx_e *a,
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}
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TRANS_FEAT(FDOT_sb_vi, aa64_f8dp4, do_f8dot_idx, a, gen_helper_gvec_fdot_idx_sb)
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+TRANS_FEAT(FDOT_hb_vi, aa64_f8dp2, do_f8dot_idx, a, gen_helper_gvec_fdot_idx_hb)
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static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,
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gen_helper_gvec_3 * const fns[2])