hw/pci-host/aspeed_pcie: Convert to DEFINE_TYPES() with inlined TypeInfo
Replace the legacy type_register_static()/type_init() registration pattern with the modern DEFINE_TYPES() macro. Inline 6 standalone TypeInfo variables (aspeed_pcie_phy_info, aspeed_2700_pcie_phy_info aspeed_pcie_root_port_info, aspeed_pcie_rc_info, aspeed_pcie_cfg_info and aspeed_2700_pcie_cfg_info directly into the 'aspeed_pcie_types[]' array, removing the need for separate declarations. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260601024959.2347639-22-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Jun 1, 2026 at 02:50 UTC
11a4f9576ad5d0581aa90ee393168c52ed4bce89
1 file changed
+41
-53
hw/pci-host/aspeed_pcie.c
+41
-53
@@ -83,13 +83,6 @@ static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
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rpc->ssid = 0x1150;
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}
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-static const TypeInfo aspeed_pcie_root_port_info = {
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- .name = TYPE_ASPEED_PCIE_ROOT_PORT,
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- .parent = TYPE_PCIE_ROOT_PORT,
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- .instance_size = sizeof(AspeedPCIERootPortState),
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- .class_init = aspeed_pcie_root_port_class_init,
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-};
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-
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/*
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* PCIe Root Complex (RC)
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*/
@@ -305,14 +298,6 @@ static void aspeed_pcie_rc_class_init(ObjectClass *klass, const void *data)
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msi_nonbroken = true;
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}
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-static const TypeInfo aspeed_pcie_rc_info = {
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- .name = TYPE_ASPEED_PCIE_RC,
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- .parent = TYPE_PCIE_HOST_BRIDGE,
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- .instance_size = sizeof(AspeedPCIERcState),
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- .instance_init = aspeed_pcie_rc_instance_init,
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- .class_init = aspeed_pcie_rc_class_init,
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-};
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-
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/*
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* PCIe Config
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*
@@ -679,15 +664,6 @@ static void aspeed_pcie_cfg_class_init(ObjectClass *klass, const void *data)
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apc->rc_rp_addr = PCI_DEVFN(8, 0);
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}
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-static const TypeInfo aspeed_pcie_cfg_info = {
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- .name = TYPE_ASPEED_PCIE_CFG,
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- .parent = TYPE_SYS_BUS_DEVICE,
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- .instance_init = aspeed_pcie_cfg_instance_init,
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- .instance_size = sizeof(AspeedPCIECfgState),
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- .class_init = aspeed_pcie_cfg_class_init,
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- .class_size = sizeof(AspeedPCIECfgClass),
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-};
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-
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static void aspeed_2700_pcie_cfg_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned int size)
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{
@@ -798,12 +774,6 @@ static void aspeed_2700_pcie_cfg_class_init(ObjectClass *klass,
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apc->rc_rp_addr = PCI_DEVFN(0, 0);
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}
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-static const TypeInfo aspeed_2700_pcie_cfg_info = {
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- .name = TYPE_ASPEED_2700_PCIE_CFG,
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- .parent = TYPE_ASPEED_PCIE_CFG,
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- .class_init = aspeed_2700_pcie_cfg_class_init,
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-};
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-
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/*
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* PCIe PHY
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*
@@ -926,14 +896,6 @@ static void aspeed_pcie_phy_class_init(ObjectClass *klass, const void *data)
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apc->nr_regs = 0x100 >> 2;
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}
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-static const TypeInfo aspeed_pcie_phy_info = {
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- .name = TYPE_ASPEED_PCIE_PHY,
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- .parent = TYPE_SYS_BUS_DEVICE,
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- .instance_size = sizeof(AspeedPCIEPhyState),
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- .class_init = aspeed_pcie_phy_class_init,
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- .class_size = sizeof(AspeedPCIEPhyClass),
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-};
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-
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static void aspeed_2700_pcie_phy_reset_hold(Object *obj, ResetType type)
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{
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AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(obj);
@@ -961,21 +923,47 @@ static void aspeed_2700_pcie_phy_class_init(ObjectClass *klass,
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apc->nr_regs = 0x800 >> 2;
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}
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-static const TypeInfo aspeed_2700_pcie_phy_info = {
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- .name = TYPE_ASPEED_2700_PCIE_PHY,
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- .parent = TYPE_ASPEED_PCIE_PHY,
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- .class_init = aspeed_2700_pcie_phy_class_init,
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-};
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+static const TypeInfo aspeed_pcie_types[] = {
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+ {
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+ .name = TYPE_ASPEED_PCIE_RC,
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+ .parent = TYPE_PCIE_HOST_BRIDGE,
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+ .instance_size = sizeof(AspeedPCIERcState),
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+ .instance_init = aspeed_pcie_rc_instance_init,
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+ .class_init = aspeed_pcie_rc_class_init,
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+ },
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+ {
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+ .name = TYPE_ASPEED_PCIE_ROOT_PORT,
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+ .parent = TYPE_PCIE_ROOT_PORT,
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+ .instance_size = sizeof(AspeedPCIERootPortState),
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+ .class_init = aspeed_pcie_root_port_class_init,
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+ },
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+ {
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+ .name = TYPE_ASPEED_PCIE_CFG,
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+ .parent = TYPE_SYS_BUS_DEVICE,
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+ .instance_init = aspeed_pcie_cfg_instance_init,
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+ .instance_size = sizeof(AspeedPCIECfgState),
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+ .class_init = aspeed_pcie_cfg_class_init,
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+ .class_size = sizeof(AspeedPCIECfgClass),
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+ },
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+ {
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+ .name = TYPE_ASPEED_PCIE_PHY,
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+ .parent = TYPE_SYS_BUS_DEVICE,
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+ .instance_size = sizeof(AspeedPCIEPhyState),
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+ .class_init = aspeed_pcie_phy_class_init,
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+ .class_size = sizeof(AspeedPCIEPhyClass),
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+ },
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+ {
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+ .name = TYPE_ASPEED_2700_PCIE_PHY,
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+ .parent = TYPE_ASPEED_PCIE_PHY,
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+ .class_init = aspeed_2700_pcie_phy_class_init,
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+ },
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+ {
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+ .name = TYPE_ASPEED_2700_PCIE_CFG,
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+ .parent = TYPE_ASPEED_PCIE_CFG,
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+ .class_init = aspeed_2700_pcie_cfg_class_init,
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+ }
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-static void aspeed_pcie_register_types(void)
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-{
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- type_register_static(&aspeed_pcie_rc_info);
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- type_register_static(&aspeed_pcie_root_port_info);
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- type_register_static(&aspeed_pcie_cfg_info);
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- type_register_static(&aspeed_2700_pcie_cfg_info);
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- type_register_static(&aspeed_pcie_phy_info);
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- type_register_static(&aspeed_2700_pcie_phy_info);
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-}
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+};
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-type_init(aspeed_pcie_register_types);
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+DEFINE_TYPES(aspeed_pcie_types)
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