hw/arm/aspeed_ast1040: Introduce I2C support
Introduce I2C controller support for the AST1040 SoC model. The I2C model type is selected from the SoC type name, allowing the AST1040 SoC to use the corresponding aspeed.i2c-ast1040 model. The I2C controller is mapped at 0x74C0F000 and uses IRQs 64 - 77, with one IRQ assigned per I2C bus. The controller DRAM link is connected to SRAM1 (HyperRAM) for DMA support. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260603040027.938816-9-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Jun 3, 2026 at 04:00 UTC
11c05e48741e1281a31df0a465c7a30e9b08ede1
1 file changed
+16
hw/arm/aspeed_ast1040.c
+16
@@ -117,6 +117,7 @@ static void aspeed_soc_ast1040_init(Object *obj)
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object_initialize_child(obj, "sgpio[*]", &s->sgpiom[i],
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"aspeed.sgpio-ast2700");
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}
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+ object_initialize_child(obj, "i2c", &s->i2c, TYPE_ASPEED_1040_I2C);
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object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
@@ -233,6 +234,21 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
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aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_SGPIOM0 + i));
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}
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+ /* I2C */
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+ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram[1]),
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+ &error_abort);
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+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
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+ return;
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+ }
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+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
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+ sc->memmap[ASPEED_DEV_I2C]);
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+ for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
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+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
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+ sc->irqmap[ASPEED_DEV_I2C] + i);
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+ /* The AST1040 I2C controller has one IRQ per bus. */
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
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+ }
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+
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/* Unimplemented peripherals */
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aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),
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"aspeed.pwm",