@samitouri / QOSamiQemu / commits / 11c2c6e025

target/riscv: Initialize DisasContext::mo_endian once

The data access endianness is constant during a translation block; rather than calling the mo_endian() method each time, initialize the DisasContext::mo_endianness field once in TranslatorOps::init_disas_context(). Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Message-ID: <20260527201348.29511-2-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Philippe Mathieu-Daudé committed May 27, 2026 at 22:13 UTC 11c2c6e025354dfa1087730a4d00ff3312ef93db

13 files changed +40 -37

target/riscv/insn_trans/trans_rva.c.inc

+2 -2

@@ -35,7 +35,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)

35 TCGv src1;

37 mop |= MO_ALIGN;

38 - mop |= mo_endian(ctx);

38 + mop |= ctx->mo_endianness;

40 decode_save_opc(ctx, 0);

41 src1 = get_address(ctx, a->rs1, 0);

@@ -65,7 +65,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)

65 TCGLabel *l2 = gen_new_label();

67 mop |= MO_ALIGN;

68 - mop |= mo_endian(ctx);

68 + mop |= ctx->mo_endianness;

70 decode_save_opc(ctx, 0);

71 src1 = get_address(ctx, a->rs1, 0);

target/riscv/insn_trans/trans_rvd.c.inc

+2 -2

@@ -60,7 +60,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)

60 } else {

61 memop |= MO_ATOM_IFALIGN;

62 }

63 - memop |= mo_endian(ctx);

63 + memop |= ctx->mo_endianness;

65 decode_save_opc(ctx, 0);

66 addr = get_address(ctx, a->rs1, a->imm);

@@ -85,7 +85,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)

85 } else {

86 memop |= MO_ATOM_IFALIGN;

87 }

88 - memop |= mo_endian(ctx);

88 + memop |= ctx->mo_endianness;

90 decode_save_opc(ctx, 0);

91 addr = get_address(ctx, a->rs1, a->imm);

target/riscv/insn_trans/trans_rvf.c.inc

+2 -2

@@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)

48 REQUIRE_FPU;

49 REQUIRE_EXT(ctx, RVF);

51 - memop |= mo_endian(ctx);

51 + memop |= ctx->mo_endianness;

52 if (ctx->cfg_ptr->ext_zama16b) {

53 memop |= MO_ATOM_WITHIN16;

54 }

@@ -71,7 +71,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)

71 REQUIRE_FPU;

72 REQUIRE_EXT(ctx, RVF);

74 - memop |= mo_endian(ctx);

74 + memop |= ctx->mo_endianness;

75 if (ctx->cfg_ptr->ext_zama16b) {

76 memop |= MO_ATOM_WITHIN16;

77 }

target/riscv/insn_trans/trans_rvi.c.inc

+4 -4

@@ -392,7 +392,7 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)

392 }

393 } else {

394 tcg_gen_qemu_ld_i128(t16, addrl, ctx->mem_idx, memop);

395 - if (mo_endian(ctx) == MO_LE) {

395 + if (ctx->mo_endianness == MO_LE) {

396 tcg_gen_extr_i128_i64(tl, th, t16);

397 } else {

398 tcg_gen_extr_i128_i64(th, tl, t16);

@@ -409,7 +409,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)

409 {

410 bool out;

411

412 - memop |= mo_endian(ctx);

412 + memop |= ctx->mo_endianness;

413 if (ctx->cfg_ptr->ext_zama16b) {

414 memop |= MO_ATOM_WITHIN16;

415 }

@@ -508,7 +508,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)

508 tcg_gen_ext_tl_i64(tl, src2l);

509 tcg_gen_ext_tl_i64(th, src2h);

510

511 - if (mo_endian(ctx) == MO_LE) {

511 + if (ctx->mo_endianness == MO_LE) {

512 tcg_gen_concat_i64_i128(t16, tl, th);

513 } else {

514 tcg_gen_concat_i64_i128(t16, th, tl);

@@ -520,7 +520,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)

520

521 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)

522 {

523 - memop |= mo_endian(ctx);

523 + memop |= ctx->mo_endianness;

524 if (ctx->cfg_ptr->ext_zama16b) {

525 memop |= MO_ATOM_WITHIN16;

526 }

target/riscv/insn_trans/trans_rvzacas.c.inc

+2 -2

@@ -76,7 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *a, MemOp mop)

76 TCGv src1 = get_address(ctx, a->rs1, 0);

77 TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2);

79 - mop |= mo_endian(ctx);

79 + mop |= ctx->mo_endianness;

80 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);

81 tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop);

@@ -121,7 +121,7 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amocas_q *a)

121 TCGv_i64 desth = get_gpr(ctx, a->rd == 0 ? 0 : a->rd + 1, EXT_NONE);

122 MemOp memop = MO_ALIGN | MO_UO;

123

124 - memop |= mo_endian(ctx);

124 + memop |= ctx->mo_endianness;

125 tcg_gen_concat_i64_i128(src2, src2l, src2h);

126 tcg_gen_concat_i64_i128(dest, destl, desth);

127 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);

target/riscv/insn_trans/trans_rvzalasr.c.inc

+2 -2

@@ -29,7 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)

29 return false;

30 }

32 - memop |= MO_ALIGN | mo_endian(ctx);

32 + memop |= MO_ALIGN | ctx->mo_endianness;

33 memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;

35 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);

@@ -79,7 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)

79 return false;

80 }

82 - memop |= MO_ALIGN | mo_endian(ctx);

82 + memop |= MO_ALIGN | ctx->mo_endianness;

83 memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;

85 /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */

target/riscv/insn_trans/trans_rvzce.c.inc

+2 -2

@@ -185,7 +185,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val)

185

186 tcg_gen_addi_tl(addr, sp, stack_adj - reg_size);

187

188 - memop |= mo_endian(ctx);

188 + memop |= ctx->mo_endianness;

189 for (i = X_Sn + 11; i >= 0; i--) {

190 if (reg_bitmap & (1 << i)) {

191 TCGv dest = dest_gpr(ctx, i);

@@ -239,7 +239,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a)

239

240 tcg_gen_subi_tl(addr, sp, reg_size);

241

242 - memop |= mo_endian(ctx);

242 + memop |= ctx->mo_endianness;

243 for (i = X_Sn + 11; i >= 0; i--) {

244 if (reg_bitmap & (1 << i)) {

245 TCGv val = get_gpr(ctx, i, EXT_NONE);

target/riscv/insn_trans/trans_rvzfh.c.inc

+2 -2

@@ -49,7 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)

49 REQUIRE_FPU;

50 REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);

52 - memop |= mo_endian(ctx);

52 + memop |= ctx->mo_endianness;

53 decode_save_opc(ctx, 0);

54 t0 = get_gpr(ctx, a->rs1, EXT_NONE);

55 if (a->imm) {

@@ -74,7 +74,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)

74 REQUIRE_FPU;

75 REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);

77 - memop |= mo_endian(ctx);

77 + memop |= ctx->mo_endianness;

78 decode_save_opc(ctx, 0);

79 t0 = get_gpr(ctx, a->rs1, EXT_NONE);

80 if (a->imm) {

target/riscv/insn_trans/trans_rvzicfiss.c.inc

+2 -2

@@ -113,7 +113,7 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_amoswap_w *a)

113 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);

114 src1 = get_address(ctx, a->rs1, 0);

115

116 - memop |= mo_endian(ctx);

116 + memop |= ctx->mo_endianness;

117 tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop);

118 gen_set_gpr(ctx, a->rd, dest);

119 return true;

@@ -143,7 +143,7 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_amoswap_w *a)

143 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);

144 src1 = get_address(ctx, a->rs1, 0);

145

146 - memop |= mo_endian(ctx);

146 + memop |= ctx->mo_endianness;

147 tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop);

148 gen_set_gpr(ctx, a->rd, dest);

149 return true;

target/riscv/insn_trans/trans_xmips.c.inc

+4 -4

@@ -47,7 +47,7 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)

47 /* Load Doubleword Pair. */

48 static bool trans_ldp(DisasContext *ctx, arg_ldp *a)

49 {

50 - MemOp memop = MO_SQ | mo_endian(ctx);

50 + MemOp memop = MO_SQ | ctx->mo_endianness;

52 REQUIRE_XMIPSLSP(ctx);

53 REQUIRE_64_OR_128BIT(ctx);

@@ -71,7 +71,7 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)

71 /* Load Word Pair. */

72 static bool trans_lwp(DisasContext *ctx, arg_lwp *a)

73 {

74 - MemOp memop = MO_SL | mo_endian(ctx);

74 + MemOp memop = MO_SL | ctx->mo_endianness;

76 REQUIRE_XMIPSLSP(ctx);

@@ -94,7 +94,7 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)

94 /* Store Doubleword Pair. */

95 static bool trans_sdp(DisasContext *ctx, arg_sdp *a)

96 {

97 - MemOp memop = MO_UQ | mo_endian(ctx);

97 + MemOp memop = MO_UQ | ctx->mo_endianness;

99 REQUIRE_XMIPSLSP(ctx);

100 REQUIRE_64_OR_128BIT(ctx);

@@ -116,7 +116,7 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)

116 /* Store Word Pair. */

117 static bool trans_swp(DisasContext *ctx, arg_swp *a)

118 {

119 - MemOp memop = MO_SL | mo_endian(ctx);

119 + MemOp memop = MO_SL | ctx->mo_endianness;

120

121 REQUIRE_XMIPSLSP(ctx);

122

target/riscv/insn_trans/trans_xthead.c.inc

+8 -8

@@ -349,7 +349,7 @@ static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,

349 TCGv_i64 rd = cpu_fpr[a->rd];

350 TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);

351

352 - memop |= mo_endian(ctx);

352 + memop |= ctx->mo_endianness;

353 tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop);

354 if ((memop & MO_SIZE) == MO_32) {

355 gen_nanbox_s(rd, rd);

@@ -370,7 +370,7 @@ static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,

370 TCGv_i64 rd = cpu_fpr[a->rd];

371 TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);

372

373 - memop |= mo_endian(ctx);

373 + memop |= ctx->mo_endianness;

374 tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop);

375

376 return true;

@@ -570,7 +570,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,

570 TCGv rd = dest_gpr(ctx, a->rd);

571 TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);

572

573 - memop |= mo_endian(ctx);

573 + memop |= ctx->mo_endianness;

574 tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);

575 tcg_gen_addi_tl(rs1, rs1, imm);

576 gen_set_gpr(ctx, a->rd, rd);

@@ -591,7 +591,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,

591 TCGv data = get_gpr(ctx, a->rd, EXT_NONE);

592 TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);

593

594 - memop |= mo_endian(ctx);

594 + memop |= ctx->mo_endianness;

595 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);

596 tcg_gen_addi_tl(rs1, rs1, imm);

597 gen_set_gpr(ctx, a->rs1, rs1);

@@ -747,7 +747,7 @@ static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,

747 TCGv rd = dest_gpr(ctx, a->rd);

748 TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);

749

750 - memop |= mo_endian(ctx);

750 + memop |= ctx->mo_endianness;

751 tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);

752 gen_set_gpr(ctx, a->rd, rd);

753

@@ -765,7 +765,7 @@ static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,

765 TCGv data = get_gpr(ctx, a->rd, EXT_NONE);

766 TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);

767

768 - memop |= mo_endian(ctx);

768 + memop |= ctx->mo_endianness;

769 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);

770

771 return true;

@@ -926,7 +926,7 @@ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,

926 addr1 = get_address(ctx, a->rs, imm);

927 addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);

928

929 - memop |= mo_endian(ctx);

929 + memop |= ctx->mo_endianness;

930 tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop);

931 tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop);

932 gen_set_gpr(ctx, a->rd1, t1);

@@ -965,7 +965,7 @@ static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,

965 addr1 = get_address(ctx, a->rs, imm);

966 addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);

967

968 - memop |= mo_endian(ctx);

968 + memop |= ctx->mo_endianness;

969 tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop);

970 tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop);

971 return true;

target/riscv/insn_trans/trans_zilsd.c.inc

+2 -2

@@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)

30 TCGv addr = get_address(ctx, a->rs1, a->imm);

31 TCGv_i64 tmp = tcg_temp_new_i64();

33 - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));

33 + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | ctx->mo_endianness);

35 if (a->rd == 0) {

36 return true;

@@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)

85 } else {

86 tcg_gen_concat_tl_i64(tmp, data_low, data_high);

87 }

88 - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));

88 + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | ctx->mo_endianness);

90 return true;

91 }

target/riscv/translate.c

+6 -3

@@ -121,6 +121,8 @@ typedef struct DisasContext {

121 bool fcfi_lp_expected;

122 /* zicfiss extension, if shadow stack was enabled during TB gen */

123 bool bcfi_enabled;

124 + /* Data endianness from MSTATUS UBE/SBE/MBE */

125 + MemOp mo_endianness;

126 } DisasContext;

127

128 static inline bool has_ext(DisasContext *ctx, uint32_t ext)

@@ -156,7 +158,7 @@ static inline MemOp mo_endian(DisasContext *ctx)

158 #define get_address_xl(ctx) ((ctx)->address_xl)

159 #endif

160

159 -#define mxl_memop(ctx) ((get_xl(ctx) + 1) | mo_endian(ctx))

161 +#define mxl_memop(ctx) ((get_xl(ctx) + 1) | (ctx)->mo_endianness)

162

163 /* The word size for this machine mode. */

164 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)

@@ -1159,7 +1161,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,

1161 TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);

1162 MemOp size = mop & MO_SIZE;

1163

1162 - mop |= mo_endian(ctx);

1164 + mop |= ctx->mo_endianness;

1165 if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) {

1166 mop |= MO_ATOM_WITHIN16;

1167 } else {

@@ -1180,7 +1182,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop)

1182 TCGv src1 = get_address(ctx, a->rs1, 0);

1183 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);

1184

1183 - mop |= mo_endian(ctx);

1185 + mop |= ctx->mo_endianness;

1186 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);

1187 tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop);

1188

@@ -1363,6 +1365,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)

1365 ctx->zero = tcg_constant_tl(0);

1366 ctx->virt_inst_excp = false;

1367 ctx->decoders = cpu->decoders;

1368 + ctx->mo_endianness = mo_endian(ctx);

1369 }

1370

1371 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)