target/arm: Update confusing comment in cpacr_write()
In cpacr_write() a comment says "In ARMv8 most bits of CPACR_EL1 are RES0", and the mask value is left at 0, implying that we enforce those RES0 bits. In fact we only enforce RES0 when ARM_FEATURE_V8 is not implemented, and for v8 and up we allow the guest to write any bits. The addition of architectural features in v8 and v9 has also resulted in the addition of new bits to CPACR_EL1, so "most bits are RES0" isn't really true any more. Update the comment to be a bit clearer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260817123838.1578060-4-peter.maydell@linaro.org
Peter Maydell committed
Aug 17, 2026 at 13:38 UTC
11dacc5b839bd5661153b5855b423c4098c0e124
1 file changed
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target/arm/helper.c
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@@ -554,7 +554,17 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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uint32_t mask = 0;
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- /* In ARMv8 most bits of CPACR_EL1 are RES0. */
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+ /*
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+ * The AArch64 view of CPACR_EL1 has a different layout to the old
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+ * AArch32 one. We also need to permit the old AArch32 bits to be
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+ * read and written so that an AArch64 EL2 hypervisor can set up
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+ * the register for an AArch32 EL1 guest. So we choose not to
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+ * enforce any RAZ/WI or RAO/WI bits for v8 based on feature
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+ * presence/absence.
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+ *
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+ * For v7 the situation is a bit simpler and there we do choose to
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+ * enforce RAZ/WI and RAO/WI.
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+ */
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if (!arm_feature(env, ARM_FEATURE_V8)) {
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/*
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* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.