target/i386/tcg: simplify return value of gen_prepare_cc
Always make reg2 valid, unify .use_reg2 and .no_setcond now that .use_reg2 is a misnomer. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini committed
Jul 22, 2026 at 09:54 UTC
1345fa46fba1abe721e9d7d5daf7061a6ead59ef
1 file changed
+27
-36
target/i386/tcg/translate.c
+27
-36
@@ -828,13 +828,21 @@ static void gen_compute_eflags(DisasContext *s)
828
set_cc_op(s, CC_OP_EFLAGS);
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}
830
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+typedef enum {
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+ /* imm is valid and reg2 is a constant */
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+ CC_PREPARE_IMM,
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+ /* imm is invalid */
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+ CC_PREPARE_REG,
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+ /* imm and reg2 are 0, and reg is known to be 0/1 */
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+ CC_PREPARE_DIRECT,
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+} CCPrepareRHS;
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+
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typedef struct CCPrepare {
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TCGCond cond;
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TCGv reg;
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TCGv reg2;
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target_ulong imm;
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- bool use_reg2;
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- bool no_setcond;
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+ CCPrepareRHS rhs_type;
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} CCPrepare;
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static CCPrepare gen_prepare_sign_nz(TCGv src, MemOp size)
@@ -871,7 +879,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
879
tcg_gen_ext_tl(s->cc_srcT, s->cc_srcT, size);
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tcg_gen_ext_tl(cpu_cc_src, cpu_cc_src, size);
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return (CCPrepare) { .cond = TCG_COND_LTU, .reg = s->cc_srcT,
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- .reg2 = cpu_cc_src, .use_reg2 = true };
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+ .reg2 = cpu_cc_src, .rhs_type = CC_PREPARE_REG };
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case CC_OP_ADDB ... CC_OP_ADDQ:
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/* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
@@ -879,7 +887,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
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tcg_gen_ext_tl(cpu_cc_dst, cpu_cc_dst, size);
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tcg_gen_ext_tl(cpu_cc_src, cpu_cc_src, size);
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return (CCPrepare) { .cond = TCG_COND_LTU, .reg = cpu_cc_dst,
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- .reg2 = cpu_cc_src, .use_reg2 = true };
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+ .reg2 = cpu_cc_src, .rhs_type = CC_PREPARE_REG };
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case CC_OP_LOGICB ... CC_OP_LOGICQ:
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case CC_OP_POPCNT:
@@ -888,7 +896,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
896
case CC_OP_INCB ... CC_OP_INCQ:
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case CC_OP_DECB ... CC_OP_DECQ:
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return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
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- .no_setcond = true };
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+ .rhs_type = CC_PREPARE_DIRECT };
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case CC_OP_SHLB ... CC_OP_SHLQ:
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/* (CC_SRC >> (DATA_BITS - 1)) & 1 */
@@ -913,7 +921,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
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case CC_OP_ADCX:
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case CC_OP_ADCOX:
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return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_dst,
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- .no_setcond = true };
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+ .rhs_type = CC_PREPARE_DIRECT };
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case CC_OP_EFLAGS:
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case CC_OP_SARB ... CC_OP_SARQ:
@@ -931,7 +939,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
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gen_helper_cc_compute_c(reg, cpu_cc_dst, cpu_cc_src,
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cpu_cc_src2, cpu_cc_op);
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return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
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- .no_setcond = true };
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+ .rhs_type = CC_PREPARE_DIRECT };
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}
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}
945
@@ -970,7 +978,7 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
978
case CC_OP_ADOX:
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case CC_OP_ADCOX:
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return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src2,
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- .no_setcond = true };
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+ .rhs_type = CC_PREPARE_DIRECT };
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case CC_OP_SBB_SELF:
983
case CC_OP_LOGICB ... CC_OP_LOGICQ:
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case CC_OP_POPCNT:
@@ -1032,7 +1040,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
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tcg_gen_ext_tl(s->cc_srcT, s->cc_srcT, size);
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tcg_gen_ext_tl(cpu_cc_src, cpu_cc_src, size);
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cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = s->cc_srcT,
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- .reg2 = cpu_cc_src, .use_reg2 = true };
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+ .reg2 = cpu_cc_src, .rhs_type = CC_PREPARE_REG };
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break;
1045
case JCC_L:
1046
cond = TCG_COND_LT;
@@ -1043,7 +1051,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
1051
tcg_gen_ext_tl(s->cc_srcT, s->cc_srcT, size | MO_SIGN);
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tcg_gen_ext_tl(cpu_cc_src, cpu_cc_src, size | MO_SIGN);
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cc = (CCPrepare) { .cond = cond, .reg = s->cc_srcT,
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- .reg2 = cpu_cc_src, .use_reg2 = true };
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+ .reg2 = cpu_cc_src, .rhs_type = CC_PREPARE_REG };
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break;
1056
1057
default:
@@ -1128,6 +1136,9 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
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break;
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}
1138
1139
+ if (cc.rhs_type != CC_PREPARE_REG) {
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+ cc.reg2 = tcg_constant_tl(cc.imm);
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+ }
1142
if (inv) {
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cc.cond = tcg_invert_cond(cc.cond);
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}
@@ -1138,7 +1149,7 @@ static void gen_neg_setcc(DisasContext *s, int b, TCGv reg)
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{
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CCPrepare cc = gen_prepare_cc(s, b, reg);
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1141
- if (cc.no_setcond) {
1152
+ if (cc.rhs_type == CC_PREPARE_DIRECT) {
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if (cc.cond == TCG_COND_EQ) {
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tcg_gen_addi_tl(reg, cc.reg, -1);
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} else {
@@ -1147,18 +1158,14 @@ static void gen_neg_setcc(DisasContext *s, int b, TCGv reg)
1158
return;
1159
}
1160
1150
- if (cc.use_reg2) {
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- tcg_gen_negsetcond_tl(cc.cond, reg, cc.reg, cc.reg2);
1152
- } else {
1153
- tcg_gen_negsetcondi_tl(cc.cond, reg, cc.reg, cc.imm);
1154
- }
1161
+ tcg_gen_negsetcond_tl(cc.cond, reg, cc.reg, cc.reg2);
1162
}
1163
1164
static void gen_setcc(DisasContext *s, int b, TCGv reg)
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{
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CCPrepare cc = gen_prepare_cc(s, b, reg);
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1161
- if (cc.no_setcond) {
1168
+ if (cc.rhs_type == CC_PREPARE_DIRECT) {
1169
if (cc.cond == TCG_COND_EQ) {
1170
tcg_gen_xori_tl(reg, cc.reg, 1);
1171
} else {
@@ -1167,11 +1174,7 @@ static void gen_setcc(DisasContext *s, int b, TCGv reg)
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return;
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}
1176
1170
- if (cc.use_reg2) {
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- tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2);
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- } else {
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- tcg_gen_setcondi_tl(cc.cond, reg, cc.reg, cc.imm);
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- }
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+ tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2);
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}
1179
1180
static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg)
@@ -1185,11 +1188,7 @@ static inline void gen_jcc_noeob(DisasContext *s, int b, TCGLabel *l1)
1188
{
1189
CCPrepare cc = gen_prepare_cc(s, b, NULL);
1190
1188
- if (cc.use_reg2) {
1189
- tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1);
1190
- } else {
1191
- tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1);
1192
- }
1191
+ tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1);
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}
1193
1194
/* Generate a conditional jump to label 'l1' according to jump opcode
@@ -1206,11 +1205,7 @@ static inline void gen_jcc(DisasContext *s, int b, TCGLabel *l1)
1205
* it's cheaper to just compute the flags)!
1206
*/
1207
gen_update_cc_op(s);
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- if (cc.use_reg2) {
1210
- tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1);
1211
- } else {
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- tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1);
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- }
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+ tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1);
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}
1210
1211
static void gen_stos(DisasContext *s, MemOp ot, TCGv dshift)
@@ -1717,10 +1712,6 @@ static void gen_cmovcc(DisasContext *s, int b, TCGv dest, TCGv src)
1712
{
1713
CCPrepare cc = gen_prepare_cc(s, b, NULL);
1714
1720
- if (!cc.use_reg2) {
1721
- cc.reg2 = tcg_constant_tl(cc.imm);
1722
- }
1723
-
1715
tcg_gen_movcond_tl(cc.cond, dest, cc.reg, cc.reg2, src, dest);
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}
1717