target/arm: Implement FMOP4 (non-widening) for float64
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260702204314.79224-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jul 2, 2026 at 13:43 UTC
13c434a796c8d5b6fd3d3df8bc6c4ea3aaaba0a2
5 files changed
+62
target/arm/cpu-features.h
+5
@@ -1812,6 +1812,11 @@ static inline bool isar_feature_aa64_sme_mop4_f16f16(const ARMISARegisters *id)
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return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f16f16(id);
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}
1814
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+static inline bool isar_feature_aa64_sme_mop4_f64f64(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f64f64(id);
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+}
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+
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
target/arm/tcg/helper-sme-defs.h
+4
@@ -363,3 +363,7 @@ DEF_HELPER_FLAGS_5(sme_ah_fmop4s_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst,
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DEF_HELPER_FLAGS_5(sme_fmop4a_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(sme_fmop4s_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(sme_ah_fmop4s_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+
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+DEF_HELPER_FLAGS_5(sme_fmop4a_dd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(sme_fmop4s_dd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(sme_ah_fmop4s_dd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
target/arm/tcg/sme.decode
+3
@@ -1098,6 +1098,9 @@ LUTI4_s_4b 1100 0000 1001 101 1 00 00 00 ....0 zd:5 \
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&mop4 zm=%mop4_zm zn=%mop4_zn
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@mop4_o2 .... .... ... m:1 .... .... .. n:1 ... . s:1 .. zad:2 \
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&mop4 zm=%mop4_zm zn=%mop4_zn
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+@mop4_o3 .... .... ... m:1 .... .... .. n:1 ... . s:1 . zad:3 \
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+ &mop4 zm=%mop4_zm zn=%mop4_zn
1103
1104
FMOP4_hh 1000 0001 000. ...0 0000 00.. ..0. 100. @mop4_o1
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FMOP4_ss 1000 0000 000. ...0 0000 00.. ..0. 00.. @mop4_o2
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+FMOP4_dd 1000 0000 110. ...0 0000 00.. ..0. 1... @mop4_o3
target/arm/tcg/sme_helper.c
+42
@@ -2719,3 +2719,45 @@ void HELPER(sme_ah_fmop4s_ss)(void *vza, void *vzn, void *vzm,
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{
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sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(float32), inner_ah_fmop4s_ss);
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}
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+
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+static void inner_fmop4a_dd(void *vd, void *vn, void *vm, void *vinfo)
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+{
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+ float64 *d = vd, *n = vn, *m = vm;
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+ float_status *fpst = vinfo;
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+
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+ *d = float64_muladd(*n, *m, *d, 0, fpst);
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+}
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+
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+void HELPER(sme_fmop4a_dd)(void *vza, void *vzn, void *vzm,
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+ float_status *fpst, uint32_t desc)
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+{
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+ sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(float64), inner_fmop4a_dd);
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+}
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+
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+static void inner_fmop4s_dd(void *vd, void *vn, void *vm, void *vinfo)
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+{
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+ float64 *d = vd, *n = vn, *m = vm;
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+ float_status *fpst = vinfo;
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+
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+ *d = float64_muladd(float64_chs(*n), *m, *d, 0, fpst);
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+}
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+
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+void HELPER(sme_fmop4s_dd)(void *vza, void *vzn, void *vzm,
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+ float_status *fpst, uint32_t desc)
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+{
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+ sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(float64), inner_fmop4s_dd);
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+}
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+
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+static void inner_ah_fmop4s_dd(void *vd, void *vn, void *vm, void *vinfo)
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+{
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+ float64 *d = vd, *n = vn, *m = vm;
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+ float_status *fpst = vinfo;
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+
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+ *d = float64_muladd(*n, *m, *d, float_muladd_negate_product, fpst);
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+}
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+
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+void HELPER(sme_ah_fmop4s_dd)(void *vza, void *vzn, void *vzm,
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+ float_status *fpst, uint32_t desc)
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+{
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+ sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(float64), inner_ah_fmop4s_dd);
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+}
target/arm/tcg/translate-sme.c
+8
@@ -2039,3 +2039,11 @@ static gen_helper_gvec_3_ptr * const fmop4_ss[3] = {
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gen_helper_sme_ah_fmop4s_ss
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};
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TRANS_FEAT(FMOP4_ss, aa64_sme_mop4, do_mop4_fp, a, MO_32, FPST_ZA, fmop4_ss)
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+
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+static gen_helper_gvec_3_ptr * const fmop4_dd[3] = {
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+ gen_helper_sme_fmop4a_dd,
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+ gen_helper_sme_fmop4s_dd,
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+ gen_helper_sme_ah_fmop4s_dd
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+};
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+TRANS_FEAT(FMOP4_dd, aa64_sme_mop4_f64f64,
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+ do_mop4_fp, a, MO_64, FPST_ZA, fmop4_dd)