target/hexagon: raise SIGBUS on unaligned data access in sysemu
hexagon-softmmu had no enforcement of alignment for scalar loads and stores: the MO_ALIGN flag added by the previous two commits triggers TLB_INVALID_MASK/alignment faults in cputlb.c, but Hexagon's TCGCPUOps did not implement do_unaligned_access, so the fault was never delivered to the guest. Add hexagon_cpu_do_unaligned_access(), which raises HEX_CAUSE_MISALIGNED_LOAD/_STORE via the existing HEX_EVENT_PRECISE path, mirroring raise_tlbmiss_exception()/raise_perm_exception(). Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Reviewed-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Jul 13, 2026 at 18:09 UTC
13eb268182476414c4604302404a08ee09b8572e
1 file changed
+25
target/hexagon/cpu.c
+25
@@ -637,6 +637,18 @@ static void raise_perm_exception(CPUState *cs, uint32_t VA, int slot,
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cs->exception_index = excp;
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}
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+static void raise_misaligned_exception(CPUState *cs, uint32_t VA, int slot,
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+ MMUAccessType access_type)
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+{
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+ CPUHexagonState *env = cpu_env(cs);
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+ int32_t excp = (access_type == MMU_DATA_STORE) ?
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+ HEX_CAUSE_MISALIGNED_STORE : HEX_CAUSE_MISALIGNED_LOAD;
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+
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+ set_badva_regs(env, VA, slot, access_type);
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+ cs->exception_index = HEX_EVENT_PRECISE;
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+ env->cause_code = excp;
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+}
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+
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static const char *access_type_names[] = { "MMU_DATA_LOAD ", "MMU_DATA_STORE",
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"MMU_INST_FETCH" };
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@@ -715,6 +727,18 @@ static vaddr hexagon_pointer_wrap(CPUState *cs, int mmu_idx,
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return result;
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}
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+static G_NORETURN
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+void hexagon_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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+ MMUAccessType access_type, int mmu_idx,
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+ uintptr_t retaddr)
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+{
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+ CPUHexagonState *env = cpu_env(cs);
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+
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+ raise_misaligned_exception(cs, addr, 0, access_type);
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+ do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC],
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+ retaddr);
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+}
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+
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#endif
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static const TCGCPUOps hexagon_tcg_ops = {
@@ -732,6 +756,7 @@ static const TCGCPUOps hexagon_tcg_ops = {
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.pointer_wrap = hexagon_pointer_wrap,
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.cpu_exec_reset = cpu_reset,
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.tlb_fill = hexagon_tlb_fill,
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+ .do_unaligned_access = hexagon_cpu_do_unaligned_access,
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.cpu_exec_halt = hexagon_cpu_has_work,
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.do_interrupt = hexagon_cpu_do_interrupt,
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#endif /* !CONFIG_USER_ONLY */