target/loongarch: Use sys_state in tcg_cpu.c when accessing CSR registers
When accessing CSR registers in file tcg_cpu.c, use sys_state rather than env. There is no function change. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@mailo.com> Tested-by: Song Gao <gaosong@loongson.cn> Message-ID: <20260605082552.175336-8-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Bibo Mao committed
Jun 5, 2026 at 16:25 UTC
15e3879769081c93988b192c88467e0441f9ae60
1 file changed
+56
-51
target/loongarch/tcg/tcg_cpu.c
+56
-51
@@ -77,34 +77,35 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env,
77
static void loongarch_cpu_do_interrupt(CPUState *cs)
78
{
79
CPULoongArchState *env = cpu_env(cs);
80
+ CPUSysState *sys = env_sys(env);
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bool update_badinstr = 1;
82
int cause = -1;
82
- bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
83
- uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
83
+ bool tlbfill = FIELD_EX64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
84
+ uint32_t vec_size = FIELD_EX64(sys->CSR_ECFG, CSR_ECFG, VS);
85
uint64_t last_pc = env->pc;
86
87
if (cs->exception_index != EXCCODE_INT) {
88
qemu_log_mask(CPU_LOG_INT,
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"%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
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" TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n",
90
- __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA,
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+ __func__, env->pc, sys->CSR_ERA, sys->CSR_TLBRERA,
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cs->exception_index,
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loongarch_exception_name(cs->exception_index));
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}
95
96
switch (cs->exception_index) {
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case EXCCODE_DBP:
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- env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
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- env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
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+ sys->CSR_DBG = FIELD_DP64(sys->CSR_DBG, CSR_DBG, DCL, 1);
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+ sys->CSR_DBG = FIELD_DP64(sys->CSR_DBG, CSR_DBG, ECODE, 0xC);
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goto set_DERA;
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set_DERA:
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- env->CSR_DERA = env->pc;
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- env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
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- set_pc(env, env->CSR_EENTRY + 0x480);
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+ sys->CSR_DERA = env->pc;
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+ sys->CSR_DBG = FIELD_DP64(sys->CSR_DBG, CSR_DBG, DST, 1);
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+ set_pc(env, sys->CSR_EENTRY + 0x480);
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break;
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case EXCCODE_INT:
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- if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
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- env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
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+ if (FIELD_EX64(sys->CSR_DBG, CSR_DBG, DST)) {
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+ sys->CSR_DBG = FIELD_DP64(sys->CSR_DBG, CSR_DBG, DEI, 1);
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goto set_DERA;
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}
111
QEMU_FALLTHROUGH;
@@ -115,7 +116,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
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update_badinstr = 0;
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break;
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case EXCCODE_BCE:
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- env->CSR_BADV = env->pc;
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+ sys->CSR_BADV = env->pc;
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QEMU_FALLTHROUGH;
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case EXCCODE_SYS:
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case EXCCODE_BRK:
@@ -142,35 +143,35 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
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if (update_badinstr) {
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MemOpIdx oi = make_memop_idx(MO_LEUL, cpu_mmu_index(cs, true));
145
145
- env->CSR_BADI = cpu_ldl_code_mmu(env, env->pc, oi, 0);
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+ sys->CSR_BADI = cpu_ldl_code_mmu(env, env->pc, oi, 0);
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}
148
149
/* Save PLV and IE */
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if (tlbfill) {
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- env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
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- FIELD_EX64(env->CSR_CRMD,
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+ sys->CSR_TLBRPRMD = FIELD_DP64(sys->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
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+ FIELD_EX64(sys->CSR_CRMD,
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CSR_CRMD, PLV));
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- env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
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- FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
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+ sys->CSR_TLBRPRMD = FIELD_DP64(sys->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
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+ FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, IE));
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/* set the DA mode */
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- env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
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- env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
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- env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
157
+ sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DA, 1);
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+ sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PG, 0);
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+ sys->CSR_TLBRERA = FIELD_DP64(sys->CSR_TLBRERA, CSR_TLBRERA,
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PC, (env->pc >> 2));
161
} else {
161
- env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
162
+ sys->CSR_ESTAT = FIELD_DP64(sys->CSR_ESTAT, CSR_ESTAT, ECODE,
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EXCODE_MCODE(cause));
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- env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
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+ sys->CSR_ESTAT = FIELD_DP64(sys->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
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EXCODE_SUBCODE(cause));
165
- env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
166
- FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
167
- env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
168
- FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
169
- env->CSR_ERA = env->pc;
166
+ sys->CSR_PRMD = FIELD_DP64(sys->CSR_PRMD, CSR_PRMD, PPLV,
167
+ FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PLV));
168
+ sys->CSR_PRMD = FIELD_DP64(sys->CSR_PRMD, CSR_PRMD, PIE,
169
+ FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, IE));
170
+ sys->CSR_ERA = env->pc;
171
}
172
172
- env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
173
- env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
173
+ sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PLV, 0);
174
+ sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, IE, 0);
175
176
if (vec_size) {
177
vec_size = (1 << vec_size) * 4;
@@ -179,27 +180,27 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
180
if (cs->exception_index == EXCCODE_INT) {
181
/* Interrupt */
182
uint32_t vector = 0;
182
- uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
183
- pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
183
+ uint32_t pending = FIELD_EX64(sys->CSR_ESTAT, CSR_ESTAT, IS);
184
+ pending &= FIELD_EX64(sys->CSR_ECFG, CSR_ECFG, LIE);
185
186
/* Find the highest-priority interrupt. */
187
vector = 31 - clz32(pending);
187
- set_pc(env, env->CSR_EENTRY + \
188
+ set_pc(env, sys->CSR_EENTRY + \
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(EXCCODE_EXTERNAL_INT + vector) * vec_size);
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qemu_log_mask(CPU_LOG_INT,
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"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
192
" cause %d\n" " A " TARGET_FMT_lx " D "
193
TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS"
194
TARGET_FMT_lx "\n",
194
- __func__, env->pc, env->CSR_ERA,
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- cause, env->CSR_BADV, env->CSR_DERA, vector,
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- env->CSR_ECFG, env->CSR_ESTAT);
195
+ __func__, env->pc, sys->CSR_ERA,
196
+ cause, sys->CSR_BADV, sys->CSR_DERA, vector,
197
+ sys->CSR_ECFG, sys->CSR_ESTAT);
198
qemu_plugin_vcpu_interrupt_cb(cs, last_pc);
199
} else {
200
if (tlbfill) {
200
- set_pc(env, env->CSR_TLBRENTRY);
201
+ set_pc(env, sys->CSR_TLBRENTRY);
202
} else {
202
- set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size);
203
+ set_pc(env, sys->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size);
204
}
205
qemu_log_mask(CPU_LOG_INT,
206
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
@@ -207,12 +208,12 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
208
" EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
209
"BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
210
" cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc,
210
- tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
211
- cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
212
- env->CSR_ECFG,
213
- tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
214
- env->CSR_BADI, env->gpr[11], cs->cpu_index,
215
- env->CSR_ASID);
211
+ tlbfill ? sys->CSR_TLBRERA : sys->CSR_ERA,
212
+ cause, tlbfill ? "(refill)" : "", sys->CSR_ESTAT,
213
+ sys->CSR_ECFG,
214
+ tlbfill ? sys->CSR_TLBRBADV : sys->CSR_BADV,
215
+ sys->CSR_BADI, env->gpr[11], cs->cpu_index,
216
+ sys->CSR_ASID);
217
qemu_plugin_vcpu_exception_cb(cs, last_pc);
218
}
219
cs->exception_index = -1;
@@ -226,8 +227,9 @@ static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
227
uintptr_t retaddr)
228
{
229
CPULoongArchState *env = cpu_env(cs);
230
+ CPUSysState *sys = env_sys(env);
231
230
- env->CSR_BADV = addr;
232
+ sys->CSR_BADV = addr;
233
if (access_type == MMU_INST_FETCH) {
234
do_raise_exception(env, EXCCODE_ADEF, retaddr);
235
} else {
@@ -238,9 +240,10 @@ static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
240
static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env)
241
{
242
bool ret = 0;
243
+ CPUSysState *sys = env_sys(env);
244
242
- ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) &&
243
- !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)));
245
+ ret = (FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, IE) &&
246
+ !(FIELD_EX64(sys->CSR_DBG, CSR_DBG, DST)));
247
248
return ret;
249
}
@@ -271,12 +274,13 @@ static vaddr loongarch_pointer_wrap(CPUState *cs, int mmu_idx,
274
static TCGTBCPUState loongarch_get_tb_cpu_state(CPUState *cs)
275
{
276
CPULoongArchState *env = cpu_env(cs);
277
+ CPUSysState *sys = env_sys(env);
278
uint32_t flags;
279
276
- flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
277
- flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
278
- flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
279
- flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
280
+ flags = sys->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
281
+ flags |= FIELD_EX64(sys->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
282
+ flags |= FIELD_EX64(sys->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
283
+ flags |= FIELD_EX64(sys->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
284
flags |= is_va32(env) * HW_FLAGS_VA32;
285
286
return (TCGTBCPUState){ .pc = env->pc, .flags = flags };
@@ -299,9 +303,10 @@ static void loongarch_restore_state_to_opc(CPUState *cs,
303
static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
304
{
305
CPULoongArchState *env = cpu_env(cs);
306
+ CPUSysState *sys = env_sys(env);
307
303
- if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
304
- return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
308
+ if (FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PG)) {
309
+ return FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PLV);
310
}
311
return MMU_DA_IDX;
312
}