@samitouri / QOSamiQemu / commits / 1645c2e028

linux-user/hppa: add coredump support

Add HAVE_ELF_CORE_DUMP, target_elf_gregset_t (80 entries matching arch/parisc/include/uapi/asm/ptrace.h), and elf_core_copy_regs(). The struct layout matches the kernel's struct user_regs_struct: gr[0..31] at indices [0..31] (PSW in gr[0]) sr[0..7] at indices [32..39] iaoq[0..1] at indices [40..41] (instruction address queue) iasq[0..1] at indices [42..43] sar at index [44] (shift amount / CR11) iir at index [45] (interrupt instruction register) isr at index [46] (interrupt space register) ior at index [47] (interrupt offset register) ipsw at index [48] (interrupt PSW / CR22) cr0 at index [49] (recovery counter) cr24_31[8] at indices [50..57] cr8_15[6] at indices [58..63] pad[16] at indices [64..79] elf_core_copy_regs() saves GRs, IAOQ (front/back), and SAR. Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Helge Deller <deller@gmx.de>

Matt Turner committed May 21, 2026 at 01:56 UTC 1645c2e028275205024abd52faec21370fc6afd7
2 files changed +34
linux-user/hppa/elfload.c
+13
@@ -16,6 +16,19 @@ const char *get_elf_platform(CPUState *cs)
16 return "PARISC";
17 }
18
19 +void elf_core_copy_regs(target_elf_gregset_t *r, const CPUArchState *env)
20 +{
21 + int i;
22 +
23 + memset(r, 0, sizeof(*r));
24 + for (i = 0; i < 32; i++) {
25 + r->gr[i] = tswapal(env->gr[i]);
26 + }
27 + r->iaoq[0] = tswapal(env->iaoq_f);
28 + r->iaoq[1] = tswapal(env->iaoq_b);
29 + r->sar = tswapal(env->cr[CR_SAR]);
30 +}
31 +
32 bool init_guest_commpage(void)
33 {
34 /* If reserved_va, then we have already mapped 0 page on the host. */
linux-user/hppa/target_elf.h
+21
@@ -12,6 +12,27 @@
12 #define ELF_MACHINE EM_PARISC
13
14 #define HAVE_ELF_PLATFORM 1
15 +#define HAVE_ELF_CORE_DUMP 1
16 +
17 +/*
18 + * Matches struct user_regs_struct from arch/parisc/include/uapi/asm/ptrace.h.
19 + * ELF_NGREG = 80; register indices match those used by libunwind and gdb.
20 + */
21 +typedef struct target_elf_gregset_t {
22 + abi_ulong gr[32]; /* gr[0..31]; PSW in gr[0] [0..31] */
23 + abi_ulong sr[8]; /* space registers [32..39] */
24 + abi_ulong iaoq[2]; /* instruction address offset [40..41] */
25 + abi_ulong iasq[2]; /* instruction address space [42..43] */
26 + abi_ulong sar; /* shift amount register (CR11) [44] */
27 + abi_ulong iir; /* interrupt instruction register [45] */
28 + abi_ulong isr; /* interrupt space register [46] */
29 + abi_ulong ior; /* interrupt offset register [47] */
30 + abi_ulong ipsw; /* interrupt PSW (CR22) [48] */
31 + abi_ulong cr0; /* recovery counter [49] */
32 + abi_ulong cr24_31[8]; /* cr24..cr31 [50..57] */
33 + abi_ulong cr8_15[6]; /* cr8, cr9, cr12, cr13, cr10, cr15 [58..63] */
34 + abi_ulong pad[16]; /* pad to 80 elements [64..79] */
35 +} target_elf_gregset_t;
36
37 #define LO_COMMPAGE 0
38 #define STACK_GROWS_DOWN 0