@samitouri / QOSamiQemu / commits / 17b9f38982

hw/pci/pci: Enforce pci_setup_iommu_per_bus() is called only once per bus

Currently it is possible to attach several arm-smmuv3 devices to the same bus although it is a wrong setup. Change the prototype of pci_setup_iommu_per_bus to pass an error handle. This latter is set when iommu_per_bus is already set and used by the single caller (smmu_base_realize) to report a useful error to the end-user. While at it document pci_setup_iommu_per_bus callback in the header. Fixes: 66d2f665e163 ("hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation") Signed-off-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nathan Chen <nathanc@nvidia.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@mailo.com> Message-id: 20260603124415.1120808-1-eric.auger@redhat.com Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Eric Auger committed Jun 3, 2026 at 14:44 UTC 17b9f38982c10cb0696bce73fcedb927aee52de1
3 files changed +25 -4
hw/arm/smmu-common.c
+3 -1
@@ -981,7 +981,9 @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
981 }
982
983 if (s->smmu_per_bus) {
984 - pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s);
984 + if (!pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s, errp)) {
985 + return;
986 + }
987 } else {
988 pci_setup_iommu(pci_bus, s->iommu_ops, s);
989 }
hw/pci/pci.c
+7 -2
@@ -3314,11 +3314,16 @@ void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque)
3314 * IOMMU ops are returned, avoiding the use of the parent’s IOMMU when
3315 * it's not appropriate.
3316 */
3317 -void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops,
3318 - void *opaque)
3317 +bool pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops,
3318 + void *opaque, Error **errp)
3319 {
3320 + if (bus->iommu_per_bus) {
3321 + error_setg(errp, "An iommu is already attached to this bus");
3322 + return false;
3323 + }
3324 pci_setup_iommu(bus, ops, opaque);
3325 bus->iommu_per_bus = true;
3326 + return true;
3327 }
3328
3329 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
include/hw/pci/pci.h
+15 -1
@@ -863,7 +863,21 @@ int pci_iommu_unregister_iotlb_notifier(PCIDevice *dev, uint32_t pasid,
863 */
864 void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque);
865
866 -void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque);
866 +/**
867 + * pci_setup_iommu_per_bus: Initialize specific IOMMU handlers for a PCIBus
868 + *
869 + * Similar to pci_setup_iommu but enforces that the iommu only protects
870 + * @bus downstream end points and no other bus hierarchy
871 + *
872 + * @bus: the #PCIBus being updated.
873 + * @ops: the #PCIIOMMUOps
874 + * @opaque: passed to callbacks of the @ops structure.
875 + * @errp: error handle
876 + *
877 + * Returns false on failure with @errp set, true on success
878 + */
879 +bool pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops,
880 + void *opaque, Error **errp);
881
882 pcibus_t pci_bar_address(PCIDevice *d,
883 int reg, uint8_t type, pcibus_t size);