target/arm: Implement ID_AA64ISAR3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260522220306.235200-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
187304a617bf9452f4882a7a5ac3513cb7d2a689
4 files changed
+17
-2
target/arm/cpu-features.h
+9
@@ -244,6 +244,15 @@ FIELD(ID_AA64ISAR2, CSSC, 52, 4)
244
FIELD(ID_AA64ISAR2, LUT, 56, 4)
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FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
246
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+FIELD(ID_AA64ISAR3, CPA, 0, 4)
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+FIELD(ID_AA64ISAR3, FAMINMAX, 4, 4)
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+FIELD(ID_AA64ISAR3, TLBIW, 8, 4)
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+FIELD(ID_AA64ISAR3, PACM, 12, 4)
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+FIELD(ID_AA64ISAR3, LSFE, 16, 4)
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+FIELD(ID_AA64ISAR3, OCCMO, 20, 4)
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+FIELD(ID_AA64ISAR3, LSUI, 24, 4)
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+FIELD(ID_AA64ISAR3, FPRCVT, 28, 4)
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+
256
FIELD(ID_AA64PFR0, EL0, 0, 4)
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FIELD(ID_AA64PFR0, EL1, 4, 4)
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FIELD(ID_AA64PFR0, EL2, 8, 4)
target/arm/cpu-sysregs.h.inc
+1
@@ -10,6 +10,7 @@ DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)
10
DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
11
DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
12
DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
13
+DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3)
14
DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
15
DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
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DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
target/arm/cpu.c
+1
@@ -1747,6 +1747,7 @@ static void arm_clear_aarch64_idregs(ARMCPU *cpu)
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SET_IDREG(&cpu->isar, ID_AA64ISAR0, 0);
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SET_IDREG(&cpu->isar, ID_AA64ISAR1, 0);
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SET_IDREG(&cpu->isar, ID_AA64ISAR2, 0);
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+ SET_IDREG(&cpu->isar, ID_AA64ISAR3, 0);
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SET_IDREG(&cpu->isar, ID_AA64PFR0, 0);
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SET_IDREG(&cpu->isar, ID_AA64PFR1, 0);
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SET_IDREG(&cpu->isar, ID_AA64PFR2, 0);
target/arm/helper.c
+6
-2
@@ -6519,11 +6519,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_tid3,
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.resetvalue = GET_IDREG(isar, ID_AA64ISAR2)},
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- { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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+ { .name = "ID_AA64ISAR3_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_tid3,
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- .resetvalue = 0 },
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+ .resetvalue = GET_IDREG(isar, ID_AA64ISAR3) },
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{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
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.access = PL1_R, .type = ARM_CP_CONST,
@@ -6752,6 +6752,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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R_ID_AA64ISAR2_BC_MASK |
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R_ID_AA64ISAR2_RPRFM_MASK |
6754
R_ID_AA64ISAR2_CSSC_MASK },
6755
+ { .name = "ID_AA64ISAR3_EL1",
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+ .exported_bits = R_ID_AA64ISAR3_FAMINMAX_MASK |
6757
+ R_ID_AA64ISAR3_LSFE_MASK |
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+ R_ID_AA64ISAR3_FPRCVT_MASK },
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{ .name = "ID_AA64ISAR*_EL1_RESERVED",
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.is_glob = true },
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};