hw/hexagon: add hex-subsys
The virt and DSP machine models build the same core subsystem, let's abstract out that part. Start with the DDR and config table ROM setup. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260806042723.3785369-2-brian.cain@oss.qualcomm.com Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Aug 5, 2026 at 21:27 UTC
197870349f2b6e5bb3ed89bf1a949ecaca09cd78
5 files changed
+54
-27
hw/hexagon/hex-subsys.c
new
+32
@@ -0,0 +1,32 @@
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+/*
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+ * Hexagon subsystem helpers shared between the machine models.
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+ *
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+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "qapi/error.h"
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+#include "hw/hexagon/hex-subsys.h"
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+#include "hw/core/loader.h"
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+#include "system/address-spaces.h"
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+
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+void hex_subsys_create(HexagonCommonMachineState *hms,
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+ const struct hexagon_machine_config *m_cfg)
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+{
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+ MachineState *machine = MACHINE(hms);
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+ MemoryRegion *sysmem = get_system_memory();
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+
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+ /* Main DDR at the reset vector. */
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+ memory_region_init_ram(&hms->ram, NULL, "ddr.ram", machine->ram_size,
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+ &error_fatal);
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+ memory_region_add_subregion(sysmem, 0x0, &hms->ram);
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+
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+ /* Config-table ROM and the blob that backs it. */
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+ memory_region_init_rom(&hms->cfgtable_rom, NULL, "config_table.rom",
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+ sizeof(m_cfg->cfgtable), &error_fatal);
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+ memory_region_add_subregion(sysmem, m_cfg->cfgbase, &hms->cfgtable_rom);
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+ rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable,
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+ sizeof(m_cfg->cfgtable), m_cfg->cfgbase,
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+ &address_space_memory);
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+}
hw/hexagon/hexagon_dsp.c
+2
-15
@@ -14,6 +14,7 @@
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#include "hw/core/boards.h"
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#include "hw/core/qdev-properties.h"
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#include "hw/hexagon/hexagon.h"
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+#include "hw/hexagon/hex-subsys.h"
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#include "hw/hexagon/hexagon_globalreg.h"
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#include "hw/hexagon/hexagon_tlb.h"
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#include "hw/core/loader.h"
@@ -108,7 +109,6 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
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{
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HexagonCommonMachineState *hms = HEXAGON_COMMON_MACHINE(machine);
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HexagonDspMachineState *dms = HEXAGON_DSP_MACHINE(machine);
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- MemoryRegion *address_space;
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DeviceState *glob_regs_dev;
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DeviceState *tlb_dev;
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@@ -120,16 +120,7 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
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machine->enable_graphics = 0;
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- address_space = get_system_memory();
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-
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- memory_region_init_rom(&hms->cfgtable_rom, NULL, "config_table.rom",
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- sizeof(m_cfg->cfgtable), &error_fatal);
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- memory_region_add_subregion(address_space, m_cfg->cfgbase,
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- &hms->cfgtable_rom);
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-
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- memory_region_init_ram(&hms->ram, NULL, "ddr.ram",
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- machine->ram_size, &error_fatal);
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- memory_region_add_subregion(address_space, 0x0, &hms->ram);
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+ hex_subsys_create(hms, m_cfg);
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glob_regs_dev = qdev_new(TYPE_HEXAGON_GLOBALREG);
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object_property_add_child(OBJECT(machine), "global-regs",
@@ -162,10 +153,6 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
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OBJECT(tlb_dev), &error_fatal);
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qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
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}
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-
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- rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable,
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- sizeof(m_cfg->cfgtable), m_cfg->cfgbase,
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- &address_space_memory);
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}
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static void init_mc(MachineClass *mc)
hw/hexagon/meson.build
+1
@@ -1,6 +1,7 @@
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hexagon_ss = ss.source_set()
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hexagon_ss.add(files('hexagon_tlb.c'))
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hexagon_ss.add(files('hexagon_globalreg.c'))
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+hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hex-subsys.c'))
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hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c'))
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hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c'))
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hw/hexagon/virt.c
+2
-12
@@ -13,6 +13,7 @@
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#include "hw/core/clock.h"
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#include "hw/core/sysbus-fdt.h"
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#include "hw/hexagon/hexagon.h"
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+#include "hw/hexagon/hex-subsys.h"
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#include "hw/hexagon/hexagon_globalreg.h"
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#include "hw/hexagon/hexagon_tlb.h"
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#include "hw/core/loader.h"
@@ -244,9 +245,7 @@ static void virt_init(MachineState *ms)
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vms->apb_clk = clock_new(OBJECT(ms), "apb-pclk");
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clock_set_hz(vms->apb_clk, 24000000);
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- memory_region_init_ram(&vms->parent_obj.ram, NULL, "ddr.ram",
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- ms->ram_size, &error_fatal);
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- memory_region_add_subregion(vms->sys, 0x0, &vms->parent_obj.ram);
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+ hex_subsys_create(&vms->parent_obj, m_cfg);
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if (m_cfg->l2tcm_size) {
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memory_region_init_ram(&vms->tcm, NULL, "tcm.ram", m_cfg->l2tcm_size,
@@ -255,11 +254,6 @@ static void virt_init(MachineState *ms)
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&vms->tcm);
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}
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- memory_region_init_rom(&vms->parent_obj.cfgtable_rom, NULL,
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- "config_table.rom", sizeof(m_cfg->cfgtable),
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- &error_fatal);
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- memory_region_add_subregion(vms->sys, m_cfg->cfgbase,
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- &vms->parent_obj.cfgtable_rom);
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fdt_add_hvx(vms, m_cfg);
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gsregs_dev = qdev_new(TYPE_HEXAGON_GLOBALREG);
@@ -302,10 +296,6 @@ static void virt_init(MachineState *ms)
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clk_phandle = fdt_add_clocks(vms);
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fdt_add_uart(vms, VIRT_UART0, clk_phandle);
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- rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable,
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- sizeof(m_cfg->cfgtable), m_cfg->cfgbase,
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- &address_space_memory);
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-
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hexagon_load_fdt(vms);
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}
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include/hw/hexagon/hex-subsys.h
new
+17
@@ -0,0 +1,17 @@
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+/*
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+ * Hexagon subsystem helpers shared between the machine models.
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+ *
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+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#ifndef HW_HEXAGON_HEX_SUBSYS_H
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+#define HW_HEXAGON_HEX_SUBSYS_H
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+
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+#include "hw/hexagon/hexagon.h"
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+
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+/* Create the subsystem shared by every Hexagon machine. */
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+void hex_subsys_create(HexagonCommonMachineState *hms,
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+ const struct hexagon_machine_config *m_cfg);
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+
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+#endif /* HW_HEXAGON_HEX_SUBSYS_H */