target/riscv: Fix size of trigger data
mcontext is at most 14 bits in size with the H extension, fix to 16 bits. trigger_cur indexes into tdata*[RV_MAX_TRIGGERS] which holds 2 elements, fix to 8 bits. This patch also adds a migration entry for mcontext which is used in tandem with other debug data that is already migrated. Note, the cpu/debug VMSTATE version is bumped, breaking migration from older versions. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-21-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
19efae275dab77a8b33a59706edfa7f81aa517ac
2 files changed
+12
-11
target/riscv/cpu.h
+5
-5
@@ -468,11 +468,11 @@ struct CPUArchState {
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target_ulong mseccfg;
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/* trigger module */
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- target_ulong trigger_cur;
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- target_ulong tdata1[RV_MAX_TRIGGERS];
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- target_ulong tdata2[RV_MAX_TRIGGERS];
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- target_ulong tdata3[RV_MAX_TRIGGERS];
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- target_ulong mcontext;
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+ uint16_t mcontext;
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+ uint8_t trigger_cur;
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+ uint64_t tdata1[RV_MAX_TRIGGERS];
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+ uint64_t tdata2[RV_MAX_TRIGGERS];
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+ uint64_t tdata3[RV_MAX_TRIGGERS];
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struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
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struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
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QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
target/riscv/machine.c
+7
-6
@@ -240,15 +240,16 @@ static int debug_post_load(void *opaque, int version_id)
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static const VMStateDescription vmstate_debug = {
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.name = "cpu/debug",
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- .version_id = 2,
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- .minimum_version_id = 2,
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+ .version_id = 3,
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+ .minimum_version_id = 3,
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.needed = debug_needed,
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.post_load = debug_post_load,
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.fields = (const VMStateField[]) {
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- VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
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- VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
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- VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
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- VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
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+ VMSTATE_UINT16(env.mcontext, RISCVCPU),
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+ VMSTATE_UINT8(env.trigger_cur, RISCVCPU),
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+ VMSTATE_UINT64_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
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+ VMSTATE_UINT64_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
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+ VMSTATE_UINT64_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
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VMSTATE_END_OF_LIST()
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}
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};