hw/i3c/dw-i3c: Add IRQ MMIO behavior
Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-13-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
1a7105014b30f19afae1df1173fe8e14760d3abb
1 file changed
+56
hw/i3c/dw-i3c.c
+56
@@ -17,6 +17,7 @@
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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+#include "hw/core/irq.h"
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REG32(DEVICE_CTRL, 0x00)
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FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1)
@@ -335,6 +336,46 @@ static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = {
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[R_SLAVE_CONFIG] = 0xffffffff,
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};
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+static void dw_i3c_update_irq(DWI3C *s)
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+{
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+ bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]);
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+ qemu_set_irq(s->irq, level);
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+}
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+
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+static uint32_t dw_i3c_intr_status_r(DWI3C *s)
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+{
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+ /* Only return the status whose corresponding EN bits are set. */
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+ return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN];
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+}
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+
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+static void dw_i3c_intr_status_w(DWI3C *s, uint32_t val)
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+{
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+ /* INTR_STATUS[13:5] is w1c, other bits are RO. */
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+ val &= 0x3fe0;
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+ s->regs[R_INTR_STATUS] &= ~val;
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+
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+ dw_i3c_update_irq(s);
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+}
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+
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+static void dw_i3c_intr_status_en_w(DWI3C *s, uint32_t val)
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+{
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+ s->regs[R_INTR_STATUS_EN] = val;
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+ dw_i3c_update_irq(s);
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+}
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+
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+static void dw_i3c_intr_signal_en_w(DWI3C *s, uint32_t val)
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+{
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+ s->regs[R_INTR_SIGNAL_EN] = val;
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+ dw_i3c_update_irq(s);
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+}
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+
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+static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val)
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+{
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+ /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */
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+ s->regs[R_INTR_STATUS] = val;
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+ dw_i3c_update_irq(s);
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+}
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+
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static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
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{
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DWI3C *s = DW_I3C(opaque);
@@ -348,6 +389,9 @@ static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
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case R_INTR_FORCE:
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value = 0;
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break;
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+ case R_INTR_STATUS:
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+ value = dw_i3c_intr_status_r(s);
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+ break;
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default:
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value = s->regs[addr];
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break;
@@ -392,6 +436,18 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,
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break;
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case R_RESET_CTRL:
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break;
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+ case R_INTR_STATUS:
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+ dw_i3c_intr_status_w(s, val32);
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+ break;
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+ case R_INTR_STATUS_EN:
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+ dw_i3c_intr_status_en_w(s, val32);
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+ break;
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+ case R_INTR_SIGNAL_EN:
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+ dw_i3c_intr_signal_en_w(s, val32);
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+ break;
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+ case R_INTR_FORCE:
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+ dw_i3c_intr_force_w(s, val32);
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+ break;
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default:
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s->regs[addr] = val32;
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break;