linux-user: add MTE_STORE_ONLY to prctl
Linux-user processes can now control whether MTE_STORE_ONLY is enabled using the prctl syscall. Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260529-feat-mte4-v7-4-ccbd3c14eb3c@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gabriel Brookman committed
May 29, 2026 at 12:52 UTC
1be42dc241322571ca5d6a54be068962d38d7dae
5 files changed
+28
-8
linux-user/aarch64/mte_user_helper.c
+10
-1
@@ -10,7 +10,7 @@
10
#include "qemu.h"
11
#include "mte_user_helper.h"
12
13
-void arm_set_mte_tcf0(CPUArchState *env, abi_long value)
13
+void arm_set_tagged_addr_ctrl(CPUArchState *env, abi_long value)
14
{
15
/*
16
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
@@ -32,4 +32,13 @@ void arm_set_mte_tcf0(CPUArchState *env, abi_long value)
32
tcf = 2;
33
}
34
env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
35
+
36
+ /*
37
+ * If MTE_STORE_ONLY is enabled, set the corresponding sctlr_el1 bit
38
+ */
39
+ if (value & PR_MTE_STORE_ONLY) {
40
+ env->cp15.sctlr_el[1] |= SCTLR_TCSO0;
41
+ } else {
42
+ env->cp15.sctlr_el[1] &= ~SCTLR_TCSO0;
43
+ }
44
}
linux-user/aarch64/mte_user_helper.h
+9
-5
@@ -20,15 +20,19 @@
20
# define PR_MTE_TAG_SHIFT 3
21
# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
22
#endif
23
+#ifndef PR_MTE_STORE_ONLY
24
+# define PR_MTE_STORE_ONLY (1UL << 19)
25
+#endif
26
27
/**
25
- * arm_set_mte_tcf0 - Set TCF0 field in SCTLR_EL1 register
28
+ * arm_set_tagged_addr_ctrl - Set TCF0 and TCSO0 fields in SCTLR_EL1 register
29
* @env: The CPU environment
27
- * @value: The value to be set for the Tag Check Fault in EL0 field.
30
+ * @value: The value to be set for the Tag Check Fault and Tag Check Store Only
31
+ * in EL0 field.
32
*
29
- * Only SYNC and ASYNC modes can be selected. If ASYMM mode is given, the SYNC
30
- * mode is selected instead. So, there is no way to set the ASYMM mode.
33
+ * Only SYNC and ASYNC modes can be selected for TCF0. If ASYMM mode is given,
34
+ * the SYNC mode is selected instead. So, there is no way to set the ASYMM mode.
35
*/
32
-void arm_set_mte_tcf0(CPUArchState *env, abi_long value);
36
+void arm_set_tagged_addr_ctrl(CPUArchState *env, abi_long value);
37
38
#endif /* AARCH64_MTE_USER_HELPER_H */
linux-user/aarch64/target_prctl.h
+5
-1
@@ -168,6 +168,9 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
168
if (cpu_isar_feature(aa64_mte, cpu)) {
169
valid_mask |= PR_MTE_TCF_MASK;
170
valid_mask |= PR_MTE_TAG_MASK;
171
+ if (cpu_isar_feature(aa64_mte_store_only, cpu)) {
172
+ valid_mask |= PR_MTE_STORE_ONLY;
173
+ }
174
}
175
176
if (arg2 & ~valid_mask) {
@@ -176,7 +179,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
179
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
180
181
if (cpu_isar_feature(aa64_mte, cpu)) {
179
- arm_set_mte_tcf0(env, arg2);
182
+ arm_set_tagged_addr_ctrl(env, arg2);
183
184
/*
185
* Write PR_MTE_TAG to GCR_EL1[Exclude].
@@ -185,6 +188,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
188
*/
189
env->cp15.gcr_el1 =
190
deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT);
191
+
192
arm_rebuild_hflags(env);
193
}
194
return 0;
target/arm/gdbstub64.c
+1
-1
@@ -684,7 +684,7 @@ int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg)
684
* expose options regarding the type of MTE fault that can be controlled at
685
* runtime.
686
*/
687
- arm_set_mte_tcf0(env, tcf);
687
+ arm_set_tagged_addr_ctrl(env, tcf);
688
689
return 1;
690
#else
tests/tcg/aarch64/mte.h
+3
@@ -20,6 +20,9 @@
20
#ifndef PR_TAGGED_ADDR_ENABLE
21
# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
22
#endif
23
+#ifndef PR_MTE_STORE_ONLY
24
+# define PR_MTE_STORE_ONLY (1UL << 19)
25
+#endif
26
#ifndef PR_MTE_TCF_SHIFT
27
# define PR_MTE_TCF_SHIFT 1
28
# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)