@samitouri / QOSamiQemu / commits / 1bfbe1fc5a

system: Make qemu_arch_available() common code

Remove the need of per-target QEMU_ARCH. Define the QEMU_ARCH_* constants based on SYS_EMU_TARGET_* ones, themselves already exposed via target_arch(), allowing to check the current target is included in @arch_bitmask. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20260213175032.32121-5-philmd@linaro.org>

Philippe Mathieu-Daudé committed Feb 13, 2026 at 15:14 UTC 1bfbe1fc5a6741fdddc64e762c20bb9b38133673
4 files changed +38 -27
include/system/arch_init.h
+34 -20
@@ -1,30 +1,44 @@
1 #ifndef QEMU_ARCH_INIT_H
2 #define QEMU_ARCH_INIT_H
3
4 +#include "qapi/qapi-types-machine.h"
5
6 enum {
6 - QEMU_ARCH_ALL = -1,
7 - QEMU_ARCH_ALPHA = (1 << 0),
8 - QEMU_ARCH_ARM = (1 << 1),
9 - QEMU_ARCH_I386 = (1 << 3),
10 - QEMU_ARCH_M68K = (1 << 4),
11 - QEMU_ARCH_MICROBLAZE = (1 << 6),
12 - QEMU_ARCH_MIPS = (1 << 7),
13 - QEMU_ARCH_PPC = (1 << 8),
14 - QEMU_ARCH_S390X = (1 << 9),
15 - QEMU_ARCH_SH4 = (1 << 10),
16 - QEMU_ARCH_SPARC = (1 << 11),
17 - QEMU_ARCH_XTENSA = (1 << 12),
18 - QEMU_ARCH_OR1K = (1 << 13),
19 - QEMU_ARCH_TRICORE = (1 << 16),
20 - QEMU_ARCH_HPPA = (1 << 18),
21 - QEMU_ARCH_RISCV = (1 << 19),
22 - QEMU_ARCH_RX = (1 << 20),
23 - QEMU_ARCH_AVR = (1 << 21),
24 - QEMU_ARCH_HEXAGON = (1 << 22),
25 - QEMU_ARCH_LOONGARCH = (1 << 23),
7 + QEMU_ARCH_ALPHA = (1UL << SYS_EMU_TARGET_ALPHA),
8 + QEMU_ARCH_ARM = (1UL << SYS_EMU_TARGET_ARM) |
9 + (1UL << SYS_EMU_TARGET_AARCH64),
10 + QEMU_ARCH_I386 = (1UL << SYS_EMU_TARGET_I386) |
11 + (1UL << SYS_EMU_TARGET_X86_64),
12 + QEMU_ARCH_M68K = (1UL << SYS_EMU_TARGET_M68K),
13 + QEMU_ARCH_MICROBLAZE = (1UL << SYS_EMU_TARGET_MICROBLAZE) |
14 + (1UL << SYS_EMU_TARGET_MICROBLAZEEL),
15 + QEMU_ARCH_MIPS = (1UL << SYS_EMU_TARGET_MIPS) |
16 + (1UL << SYS_EMU_TARGET_MIPSEL) |
17 + (1UL << SYS_EMU_TARGET_MIPS64) |
18 + (1UL << SYS_EMU_TARGET_MIPS64EL),
19 + QEMU_ARCH_PPC = (1UL << SYS_EMU_TARGET_PPC) |
20 + (1UL << SYS_EMU_TARGET_PPC64),
21 + QEMU_ARCH_S390X = (1UL << SYS_EMU_TARGET_S390X),
22 + QEMU_ARCH_SH4 = (1UL << SYS_EMU_TARGET_SH4) |
23 + (1UL << SYS_EMU_TARGET_SH4EB),
24 + QEMU_ARCH_SPARC = (1UL << SYS_EMU_TARGET_SPARC) |
25 + (1UL << SYS_EMU_TARGET_SPARC64),
26 + QEMU_ARCH_XTENSA = (1UL << SYS_EMU_TARGET_XTENSA) |
27 + (1UL << SYS_EMU_TARGET_XTENSAEB),
28 + QEMU_ARCH_OR1K = (1UL << SYS_EMU_TARGET_OR1K),
29 + QEMU_ARCH_TRICORE = (1UL << SYS_EMU_TARGET_TRICORE),
30 + QEMU_ARCH_HPPA = (1UL << SYS_EMU_TARGET_HPPA),
31 + QEMU_ARCH_RISCV = (1UL << SYS_EMU_TARGET_RISCV32) |
32 + (1UL << SYS_EMU_TARGET_RISCV64),
33 + QEMU_ARCH_RX = (1UL << SYS_EMU_TARGET_RX),
34 + QEMU_ARCH_AVR = (1UL << SYS_EMU_TARGET_AVR),
35 + QEMU_ARCH_HEXAGON = (1UL << SYS_EMU_TARGET_HEXAGON),
36 + QEMU_ARCH_LOONGARCH = (1UL << SYS_EMU_TARGET_LOONGARCH64),
37 + QEMU_ARCH_ALL = UINT32_MAX,
38 };
39
40 +QEMU_BUILD_BUG_ON(SYS_EMU_TARGET__MAX > 32);
41 +
42 /**
43 * qemu_arch_available:
44 * @arch_bitmask: bitmask of QEMU_ARCH_* constants
meson.build
-2
@@ -3375,8 +3375,6 @@ foreach target : target_dirs
3375 config_target_data.set(k, v)
3376 endif
3377 endforeach
3378 - config_target_data.set('QEMU_ARCH',
3379 - 'QEMU_ARCH_' + config_target['TARGET_BASE_ARCH'].to_upper())
3378 config_target_h += {target: configure_file(output: target + '-config-target.h',
3379 configuration: config_target_data)}
3380
system/arch_init.c
+3 -1
@@ -23,8 +23,10 @@
23 */
24 #include "qemu/osdep.h"
25 #include "system/arch_init.h"
26 +#include "qemu/bitops.h"
27 +#include "qemu/target-info-qapi.h"
28
29 bool qemu_arch_available(uint32_t arch_bitmask)
30 {
29 - return arch_bitmask & QEMU_ARCH;
31 + return extract32(arch_bitmask, target_arch(), 1);
32 }
system/meson.build
+1 -4
@@ -1,12 +1,9 @@
1 -specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files(
2 - 'arch_init.c',
3 -)])
4 -
1 system_ss.add(files(
2 'vl.c',
3 ), sdl, libpmem, libdaxctl)
4
5 system_ss.add(files(
6 + 'arch_init.c',
7 'balloon.c',
8 'bootdevice.c',
9 'cpus.c',