@samitouri / QOSamiQemu / commits / 1d8416f58a

hw/arm/aspeed_ast1040: Reuse AST2700 watchdog models

Instantiate and realize the watchdog models for the AST1040 SoC. The AST1040 watchdog controller is compatible with the AST2700 watchdog controller, so reuse the existing AST2700 watchdog model. Configure the AST1040 SoC with 8 watchdog instances and map them to their corresponding MMIO regions. The first watchdog controller (WDT0) is located at 0x74c37000, with subsequent watchdogs placed according to the controller register space size. Each watchdog is linked to the SCU device before realization to provide the required reset and system control interactions. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260603040027.938816-11-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>

Jamin Lin committed Jun 3, 2026 at 04:00 UTC 1d8416f58a92af4f4166f8fbd18fd97c5979ee6e
1 file changed +19
hw/arm/aspeed_ast1040.c
+19
@@ -119,6 +119,11 @@ static void aspeed_soc_ast1040_init(Object *obj)
119 }
120 object_initialize_child(obj, "i2c", &s->i2c, TYPE_ASPEED_1040_I2C);
121
122 + for (i = 0; i < sc->wdts_num; i++) {
123 + object_initialize_child(obj, "wdt[*]", &s->wdt[i],
124 + "aspeed.wdt-ast2700");
125 + }
126 +
127 object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
128 object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
129 object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
@@ -249,6 +254,19 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
254 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
255 }
256
257 + /* Watch dog */
258 + for (i = 0; i < sc->wdts_num; i++) {
259 + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
260 + hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
261 +
262 + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
263 + &error_abort);
264 + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
265 + return;
266 + }
267 + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
268 + }
269 +
270 /* Unimplemented peripherals */
271 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),
272 "aspeed.pwm",
@@ -290,6 +308,7 @@ static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
308 sc->sram_size[1] = 16 * MiB; /* Hyper RAM */
309 sc->uarts_num = 13;
310 sc->sgpio_num = 2;
311 + sc->wdts_num = 8;
312 sc->uarts_base = ASPEED_DEV_UART0;
313 sc->irqmap = aspeed_soc_ast1040_irqmap;
314 sc->memmap = aspeed_soc_ast1040_memmap;