target/riscv/cpu.c: add 'svbare' satp-mode

Seems like we forgot to add a flag to set satp-mode=bare. What we're doing instead is to set the CPU default satp-mode to 'off' to set it to bare ... assuming we know the default satp-mode. Otherwise one needs to do -cpu X,sv39=off,sv48=off,sv57=off,sv64=off to get a bare-mode CPU. Add a flag to make this process easier. The name choice is based on the fact that I didn't find many references to 'mbare' in RISC-V docs, but 'svbare' is a flag name that toolchain uses to set satp-mode=bare. Might as well use the same name to help with cross project compat. After this patch: $ ./build/qemu-system-riscv64 -M virt,dumpdtb=fdt.dtb -cpu rv64 $ dtc -I dtb -O dts fdt.dtb | grep mmu-type mmu-type = "riscv,sv57"; $ ./build/qemu-system-riscv64 -M virt,dumpdtb=fdt.dtb -cpu rv64,svbare=on $ dtc -I dtb -O dts fdt.dtb | grep mmu-type mmu-type = "riscv,none"; Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260611162223.2361941-2-daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>