target/arm: Implement FEAT_FAMINMAX for SME
Since there is no bfloat16 variant of FAMINMAX, check for missing function pointer in do_z2z_nn_fpst. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260522220306.235200-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
1de033cf3e0872ec2b9b6cdec1a33ad81b8bf4d6
3 files changed
+31
-2
target/arm/cpu-features.h
+5
@@ -1593,6 +1593,11 @@ static inline bool isar_feature_aa64_sme2_f64f64(const ARMISARegisters *id)
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return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_f64f64(id);
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}
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+static inline bool isar_feature_aa64_sme2_faminmax(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme2(id) && isar_feature_aa64_faminmax(id);
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+}
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+
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static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
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{
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return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id);
target/arm/tcg/sme.decode
+5
@@ -286,6 +286,11 @@ URSHL_nn 1100000 1 .. 1 ..... 1011.0 10001 .... 1 @z2z_4x4
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SQDMULH_nn 1100000 1 .. 1 ..... 1011.1 00000 .... 0 @z2z_2x2
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SQDMULH_nn 1100000 1 .. 1 ..... 1011.1 00000 .... 0 @z2z_4x4
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+FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_2x2
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+FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_4x4
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+FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2
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+FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4
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+
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### SME2 Multi-vector Multiple and Single Array Vectors
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&azz_n n off rv zn zm
target/arm/tcg/translate-sme.c
+21
-2
@@ -19,6 +19,7 @@
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#include "qemu/osdep.h"
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#include "cpu.h"
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+#include "helper-a64.h"
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#include "helper-sme.h"
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#include "helper-sve.h"
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#include "translate.h"
@@ -742,9 +743,12 @@ static bool do_z2z_nn_fpst(DisasContext *s, arg_z2z_en *a,
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gen_helper_gvec_3_ptr * const fns[4])
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{
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int esz = a->esz, n, dn, dm, vsz;
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- gen_helper_gvec_3_ptr *fn;
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+ gen_helper_gvec_3_ptr *fn = fns[esz];
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TCGv_ptr fpst;
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+ if (fn == NULL) {
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+ return false;
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+ }
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if (esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {
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return false;
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}
@@ -753,7 +757,6 @@ static bool do_z2z_nn_fpst(DisasContext *s, arg_z2z_en *a,
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}
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fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);
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- fn = fns[esz];
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n = a->n;
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dn = a->zdn;
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dm = a->zm;
@@ -812,6 +815,22 @@ static gen_helper_gvec_3_ptr * const f_vector_fminnm[4] = {
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TRANS_FEAT(FMINNM_n1, aa64_sme2, do_z2z_n1_fpst, a, f_vector_fminnm)
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TRANS_FEAT(FMINNM_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fminnm)
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+static gen_helper_gvec_3_ptr * const f_vector_famax[4] = {
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+ NULL,
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+ gen_helper_gvec_famax_h,
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+ gen_helper_gvec_famax_s,
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+ gen_helper_gvec_famax_d,
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+};
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+TRANS_FEAT(FAMAX_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famax)
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+
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+static gen_helper_gvec_3_ptr * const f_vector_famin[4] = {
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+ NULL,
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+ gen_helper_gvec_famin_h,
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+ gen_helper_gvec_famin_s,
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+ gen_helper_gvec_famin_d,
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+};
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+TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famin)
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+
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/* Add/Sub vector Z[m] to each Z[n*N] with result in ZA[d*N]. */
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static bool do_azz_n1(DisasContext *s, arg_azz_n *a, int esz,
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GVecGen3FnVar *fn)