target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type
Commit 676624d757a ("target/arm/tcg: refine cache descriptions with a wrapper") added the make_ccsidr() helper. Use it. Besides being simpler to review, it also makes arm_max_initfn() more in line which aarch64_a57_initfn(), which it almost duplicates. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20260526203722.79463-11-philmd@linaro.org>
Philippe Mathieu-Daudé committed
May 13, 2026 at 11:25 UTC
1fa6375af2454e7cb1ccdd731cfd02498a37b432
1 file changed
+7
-3
target/arm/tcg/cpu32.c
+7
-3
@@ -9,6 +9,7 @@
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*/
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#include "qemu/osdep.h"
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+#include "qemu/units.h"
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#include "cpu.h"
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#include "accel/tcg/cpu-ops.h"
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#include "internals.h"
@@ -756,9 +757,12 @@ static void arm_max_initfn(Object *obj)
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SET_IDREG(isar, ID_ISAR6, 0);
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cpu->isar.reset_pmcr_el0 = 0x41013000;
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SET_IDREG(isar, CLIDR, 0x0a200023);
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- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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- cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
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+ /* 32KB L1 dcache */
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+ cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
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+ /* 48KB L1 icache */
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+ cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
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+ /* 2048KB L2 cache */
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+ cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
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define_cortex_a72_a57_a53_cp_reginfo(cpu);
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aa32_max_features(cpu);