hw/arm: Remove the deprecated "highbank" and "midway" machines
These machines have been marked as deprecated two releases ago, and so far nobody complained that they are still useful, so it's time to remove these now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260226090704.27699-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Thomas Huth committed
Mar 6, 2026 at 09:01 UTC
201245a6542983d4c3ae8db519d9721d64afc2be
9 files changed
+7
-458
MAINTAINERS
-9
@@ -833,15 +833,6 @@ F: include/hw/*/exynos*
833
F: docs/system/arm/exynos.rst
834
F: tests/functional/arm/test_smdkc210.py
835
836
-Calxeda Highbank
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-M: Rob Herring <robh@kernel.org>
838
-M: Peter Maydell <peter.maydell@linaro.org>
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-L: qemu-arm@nongnu.org
840
-S: Odd Fixes
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-F: hw/arm/highbank.c
842
-F: hw/net/xgmac.c
843
-F: docs/system/arm/highbank.rst
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-
836
Canon DIGIC
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M: Antony Pavlov <antonynpavlov@gmail.com>
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M: Peter Maydell <peter.maydell@linaro.org>
configs/devices/arm-softmmu/default.mak
-1
@@ -12,7 +12,6 @@
12
# keep out of the build.
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# CONFIG_CUBIEBOARD=n
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# CONFIG_EXYNOS4=n
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-# CONFIG_HIGHBANK=n
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# CONFIG_INTEGRATOR=n
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# CONFIG_FSL_IMX31=n
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# CONFIG_MUSICPAL=n
docs/about/deprecated.rst
-7
@@ -293,13 +293,6 @@ they want to use and avoids confusion. Existing users of the ``spike``
293
machine must ensure that they're setting the ``spike`` machine in the
294
command line (``-M spike``).
295
296
-Arm ``highbank`` and ``midway`` machines (since 10.1)
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-'''''''''''''''''''''''''''''''''''''''''''''''''''''
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-
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-There are no known users left for these machines (if you still use it,
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-please write a mail to the qemu-devel mailing list). If you just want to
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-boot a Cortex-A15 or Cortex-A9 Linux, use the ``virt`` machine instead.
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-
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297
Backend options
298
---------------
docs/about/removed-features.rst
+7
@@ -1180,6 +1180,13 @@ and serves as the initial engineering sample rather than a production version.
1180
A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should
1181
replace the older A0 version.
1182
1183
+Arm ``highbank`` and ``midway`` machines (removed in 11.0)
1184
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
1185
+
1186
+There were no known users left for these machines. If you just want to
1187
+boot a Cortex-A15 or Cortex-A9 Linux, use the ``virt`` machine instead.
1188
+
1189
+
1190
linux-user mode CPUs
1191
--------------------
1192
docs/system/arm/highbank.rst
deleted
-19
@@ -1,19 +0,0 @@
1
-Calxeda Highbank and Midway (``highbank``, ``midway``)
2
-======================================================
3
-
4
-``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
5
-which has four Cortex-A9 cores.
6
-
7
-``midway`` is a model of the Calxeda Midway (ECX-2000) system,
8
-which has four Cortex-A15 cores.
9
-
10
-Emulated devices:
11
-
12
-- L2x0 cache controller
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-- SP804 dual timer
14
-- PL011 UART
15
-- PL061 GPIOs
16
-- PL031 RTC
17
-- PL022 synchronous serial port controller
18
-- AHCI
19
-- XGMAC ethernet controllers
docs/system/target-arm.rst
-1
@@ -83,7 +83,6 @@ Board-specific documentation
83
arm/bananapi_m2u.rst
84
arm/b-l475e-iot01a.rst
85
arm/sabrelite
86
- arm/highbank
86
arm/digic
87
arm/cubieboard
88
arm/emcraft-sf2
hw/arm/Kconfig
-16
@@ -64,22 +64,6 @@ config EXYNOS4
64
select USB_EHCI_SYSBUS
65
select OR_IRQ
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67
-config HIGHBANK
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- bool
69
- default y
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- depends on TCG && ARM
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- select A9MPCORE
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- select A15MPCORE
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- select AHCI_SYSBUS
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- select ARM_TIMER # sp804
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- select ARM_V7M
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- select PL011 # UART
77
- select PL022 # SPI
78
- select PL031 # RTC
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- select PL061 # GPIO
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- select PL310 # cache controller
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- select XGMAC # ethernet
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-
67
config INTEGRATOR
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bool
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default y
hw/arm/highbank.c
deleted
-404
@@ -1,404 +0,0 @@
1
-/*
2
- * Calxeda Highbank SoC emulation
3
- *
4
- * Copyright (c) 2010-2012 Calxeda
5
- *
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- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms and conditions of the GNU General Public License,
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- * version 2 or later, as published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
- * more details.
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- *
15
- * You should have received a copy of the GNU General Public License along with
16
- * this program. If not, see <http://www.gnu.org/licenses/>.
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- *
18
- */
19
-
20
-#include "qemu/osdep.h"
21
-#include "qemu/datadir.h"
22
-#include "qapi/error.h"
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-#include "hw/core/sysbus.h"
24
-#include "migration/vmstate.h"
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-#include "hw/arm/boot.h"
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-#include "hw/arm/machines-qom.h"
27
-#include "hw/core/loader.h"
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-#include "net/net.h"
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-#include "system/runstate.h"
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-#include "system/system.h"
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-#include "hw/core/boards.h"
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-#include "qemu/error-report.h"
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-#include "hw/char/pl011.h"
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-#include "hw/ide/ahci-sysbus.h"
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-#include "hw/cpu/a9mpcore.h"
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-#include "hw/cpu/a15mpcore.h"
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-#include "qemu/log.h"
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-#include "qom/object.h"
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-#include "cpu.h"
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-#include "target/arm/cpu-qom.h"
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-
42
-#define SMP_BOOT_ADDR 0x100
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-#define SMP_BOOT_REG 0x40
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-#define MPCORE_PERIPHBASE 0xfff10000
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-
46
-#define MVBAR_ADDR 0x200
47
-#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
48
-
49
-#define GIC_EXT_IRQS 128 /* EnergyCore ECX-1000 & ECX-2000 */
50
-
51
-/* Board init. */
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-
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-#define NUM_REGS 0x200
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-static void hb_regs_write(void *opaque, hwaddr offset,
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- uint64_t value, unsigned size)
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-{
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- uint32_t *regs = opaque;
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-
59
- if (offset == 0xf00) {
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- if (value == 1 || value == 2) {
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- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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- } else if (value == 3) {
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- qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
64
- }
65
- }
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-
67
- if (offset / 4 >= NUM_REGS) {
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- qemu_log_mask(LOG_GUEST_ERROR,
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- "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
70
- return;
71
- }
72
- regs[offset / 4] = value;
73
-}
74
-
75
-static uint64_t hb_regs_read(void *opaque, hwaddr offset,
76
- unsigned size)
77
-{
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- uint32_t value;
79
- uint32_t *regs = opaque;
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-
81
- if (offset / 4 >= NUM_REGS) {
82
- qemu_log_mask(LOG_GUEST_ERROR,
83
- "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
84
- return 0;
85
- }
86
- value = regs[offset / 4];
87
-
88
- if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
89
- value |= 0x30000000;
90
- }
91
-
92
- return value;
93
-}
94
-
95
-static const MemoryRegionOps hb_mem_ops = {
96
- .read = hb_regs_read,
97
- .write = hb_regs_write,
98
- .endianness = DEVICE_NATIVE_ENDIAN,
99
-};
100
-
101
-#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
102
-OBJECT_DECLARE_SIMPLE_TYPE(HighbankRegsState, HIGHBANK_REGISTERS)
103
-
104
-struct HighbankRegsState {
105
- /*< private >*/
106
- SysBusDevice parent_obj;
107
- /*< public >*/
108
-
109
- MemoryRegion iomem;
110
- uint32_t regs[NUM_REGS];
111
-};
112
-
113
-static const VMStateDescription vmstate_highbank_regs = {
114
- .name = "highbank-regs",
115
- .version_id = 0,
116
- .minimum_version_id = 0,
117
- .fields = (const VMStateField[]) {
118
- VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
119
- VMSTATE_END_OF_LIST(),
120
- },
121
-};
122
-
123
-static void highbank_regs_reset(DeviceState *dev)
124
-{
125
- HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
126
-
127
- s->regs[0x40] = 0x05F20121;
128
- s->regs[0x41] = 0x2;
129
- s->regs[0x42] = 0x05F30121;
130
- s->regs[0x43] = 0x05F40121;
131
-}
132
-
133
-static void highbank_regs_init(Object *obj)
134
-{
135
- HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
136
- SysBusDevice *dev = SYS_BUS_DEVICE(obj);
137
-
138
- memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
139
- "highbank_regs", 0x1000);
140
- sysbus_init_mmio(dev, &s->iomem);
141
-}
142
-
143
-static void highbank_regs_class_init(ObjectClass *klass, const void *data)
144
-{
145
- DeviceClass *dc = DEVICE_CLASS(klass);
146
-
147
- dc->desc = "Calxeda Highbank registers";
148
- dc->vmsd = &vmstate_highbank_regs;
149
- device_class_set_legacy_reset(dc, highbank_regs_reset);
150
-}
151
-
152
-static const TypeInfo highbank_regs_info = {
153
- .name = TYPE_HIGHBANK_REGISTERS,
154
- .parent = TYPE_SYS_BUS_DEVICE,
155
- .instance_size = sizeof(HighbankRegsState),
156
- .instance_init = highbank_regs_init,
157
- .class_init = highbank_regs_class_init,
158
-};
159
-
160
-static void highbank_regs_register_types(void)
161
-{
162
- type_register_static(&highbank_regs_info);
163
-}
164
-
165
-type_init(highbank_regs_register_types)
166
-
167
-static struct arm_boot_info highbank_binfo;
168
-
169
-enum cxmachines {
170
- CALXEDA_HIGHBANK,
171
- CALXEDA_MIDWAY,
172
-};
173
-
174
-/* ram_size must be set to match the upper bound of memory in the
175
- * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
176
- * normally 0xff900000 or -m 4089. When running this board on a
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- * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
178
- * device tree and pass -m 2047 to QEMU.
179
- */
180
-static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
181
-{
182
- DeviceState *dev = NULL;
183
- SysBusDevice *busdev;
184
- qemu_irq pic[GIC_EXT_IRQS];
185
- int n;
186
- unsigned int smp_cpus = machine->smp.cpus;
187
- qemu_irq cpu_irq[4];
188
- qemu_irq cpu_fiq[4];
189
- qemu_irq cpu_virq[4];
190
- qemu_irq cpu_vfiq[4];
191
- MemoryRegion *sysram;
192
- MemoryRegion *sysmem;
193
- char *sysboot_filename;
194
-
195
- switch (machine_id) {
196
- case CALXEDA_HIGHBANK:
197
- machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
198
- break;
199
- case CALXEDA_MIDWAY:
200
- machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
201
- break;
202
- default:
203
- g_assert_not_reached();
204
- }
205
-
206
- for (n = 0; n < smp_cpus; n++) {
207
- Object *cpuobj;
208
- ARMCPU *cpu;
209
-
210
- cpuobj = object_new(machine->cpu_type);
211
- cpu = ARM_CPU(cpuobj);
212
-
213
- object_property_add_child(OBJECT(machine), "cpu[*]", cpuobj);
214
- object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC,
215
- &error_abort);
216
-
217
- if (object_property_find(cpuobj, "reset-cbar")) {
218
- object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
219
- &error_abort);
220
- }
221
- qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
222
- cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
223
- cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
224
- cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
225
- cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
226
- }
227
-
228
- sysmem = get_system_memory();
229
- /* SDRAM at address zero. */
230
- memory_region_add_subregion(sysmem, 0, machine->ram);
231
-
232
- sysram = g_new(MemoryRegion, 1);
233
- memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
234
- &error_fatal);
235
- memory_region_add_subregion(sysmem, 0xfff88000, sysram);
236
- if (machine->firmware != NULL) {
237
- sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
238
- if (sysboot_filename != NULL) {
239
- if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000,
240
- NULL) < 0) {
241
- error_report("Unable to load %s", machine->firmware);
242
- exit(1);
243
- }
244
- g_free(sysboot_filename);
245
- } else {
246
- error_report("Unable to find %s", machine->firmware);
247
- exit(1);
248
- }
249
- }
250
-
251
- switch (machine_id) {
252
- case CALXEDA_HIGHBANK:
253
- dev = qdev_new("l2x0");
254
- busdev = SYS_BUS_DEVICE(dev);
255
- sysbus_realize_and_unref(busdev, &error_fatal);
256
- sysbus_mmio_map(busdev, 0, 0xfff12000);
257
-
258
- dev = qdev_new(TYPE_A9MPCORE_PRIV);
259
- break;
260
- case CALXEDA_MIDWAY:
261
- dev = qdev_new(TYPE_A15MPCORE_PRIV);
262
- break;
263
- }
264
- qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
265
- qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);
266
- busdev = SYS_BUS_DEVICE(dev);
267
- sysbus_realize_and_unref(busdev, &error_fatal);
268
- sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
269
- for (n = 0; n < smp_cpus; n++) {
270
- sysbus_connect_irq(busdev, n, cpu_irq[n]);
271
- sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
272
- sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
273
- sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
274
- }
275
-
276
- for (n = 0; n < GIC_EXT_IRQS; n++) {
277
- pic[n] = qdev_get_gpio_in(dev, n);
278
- }
279
-
280
- dev = qdev_new("sp804");
281
- qdev_prop_set_uint32(dev, "freq0", 150000000);
282
- qdev_prop_set_uint32(dev, "freq1", 150000000);
283
- busdev = SYS_BUS_DEVICE(dev);
284
- sysbus_realize_and_unref(busdev, &error_fatal);
285
- sysbus_mmio_map(busdev, 0, 0xfff34000);
286
- sysbus_connect_irq(busdev, 0, pic[18]);
287
- pl011_create(0xfff36000, pic[20], serial_hd(0));
288
-
289
- dev = qdev_new(TYPE_HIGHBANK_REGISTERS);
290
- busdev = SYS_BUS_DEVICE(dev);
291
- sysbus_realize_and_unref(busdev, &error_fatal);
292
- sysbus_mmio_map(busdev, 0, 0xfff3c000);
293
-
294
- sysbus_create_simple("pl061", 0xfff30000, pic[14]);
295
- sysbus_create_simple("pl061", 0xfff31000, pic[15]);
296
- sysbus_create_simple("pl061", 0xfff32000, pic[16]);
297
- sysbus_create_simple("pl061", 0xfff33000, pic[17]);
298
- sysbus_create_simple("pl031", 0xfff35000, pic[19]);
299
- sysbus_create_simple("pl022", 0xfff39000, pic[23]);
300
-
301
- sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
302
-
303
- dev = qemu_create_nic_device("xgmac", true, NULL);
304
- if (dev) {
305
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
306
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
307
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
308
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
309
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
310
- }
311
-
312
- dev = qemu_create_nic_device("xgmac", true, NULL);
313
- if (dev) {
314
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
315
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
316
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
317
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
318
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
319
- }
320
-
321
- /* TODO create and connect IDE devices for ide_drive_get() */
322
-
323
- highbank_binfo.ram_size = machine->ram_size;
324
- /* highbank requires a dtb in order to boot, and the dtb will override
325
- * the board ID. The following value is ignored, so set it to -1 to be
326
- * clear that the value is meaningless.
327
- */
328
- highbank_binfo.board_id = -1;
329
- highbank_binfo.loader_start = 0;
330
- highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
331
- highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
332
-
333
- arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
334
-}
335
-
336
-static void highbank_init(MachineState *machine)
337
-{
338
- calxeda_init(machine, CALXEDA_HIGHBANK);
339
-}
340
-
341
-static void midway_init(MachineState *machine)
342
-{
343
- calxeda_init(machine, CALXEDA_MIDWAY);
344
-}
345
-
346
-static void highbank_class_init(ObjectClass *oc, const void *data)
347
-{
348
- static const char * const valid_cpu_types[] = {
349
- ARM_CPU_TYPE_NAME("cortex-a9"),
350
- NULL
351
- };
352
- MachineClass *mc = MACHINE_CLASS(oc);
353
-
354
- mc->desc = "Calxeda Highbank (ECX-1000)";
355
- mc->init = highbank_init;
356
- mc->valid_cpu_types = valid_cpu_types;
357
- mc->block_default_type = IF_IDE;
358
- mc->units_per_default_bus = 1;
359
- mc->max_cpus = 4;
360
- mc->ignore_memory_transaction_failures = true;
361
- mc->default_ram_id = "highbank.dram";
362
- mc->deprecation_reason = "no known users left for this machine";
363
-}
364
-
365
-static const TypeInfo highbank_type = {
366
- .name = MACHINE_TYPE_NAME("highbank"),
367
- .parent = TYPE_MACHINE,
368
- .class_init = highbank_class_init,
369
- .interfaces = arm_machine_interfaces,
370
-};
371
-
372
-static void midway_class_init(ObjectClass *oc, const void *data)
373
-{
374
- static const char * const valid_cpu_types[] = {
375
- ARM_CPU_TYPE_NAME("cortex-a15"),
376
- NULL
377
- };
378
- MachineClass *mc = MACHINE_CLASS(oc);
379
-
380
- mc->desc = "Calxeda Midway (ECX-2000)";
381
- mc->init = midway_init;
382
- mc->valid_cpu_types = valid_cpu_types;
383
- mc->block_default_type = IF_IDE;
384
- mc->units_per_default_bus = 1;
385
- mc->max_cpus = 4;
386
- mc->ignore_memory_transaction_failures = true;
387
- mc->default_ram_id = "highbank.dram";
388
- mc->deprecation_reason = "no known users left for this machine";
389
-}
390
-
391
-static const TypeInfo midway_type = {
392
- .name = MACHINE_TYPE_NAME("midway"),
393
- .parent = TYPE_MACHINE,
394
- .class_init = midway_class_init,
395
- .interfaces = arm_machine_interfaces,
396
-};
397
-
398
-static void calxeda_machines_init(void)
399
-{
400
- type_register_static(&highbank_type);
401
- type_register_static(&midway_type);
402
-}
403
-
404
-type_init(calxeda_machines_init)
hw/arm/meson.build
-1
@@ -4,7 +4,6 @@ arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
4
arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
5
arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
6
arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
7
-arm_common_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
7
arm_common_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
8
arm_common_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
9
arm_common_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))