hw/arm: ax3000-soc: Enable Axiado SD host controller
Enable SD host controller into Axiado AX3000 SoC to load kernel and rootfs from eMMC. Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260713073033.3883619-6-kchiu@axiado.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Kuan-Jui Chiu committed
Aug 11, 2026 at 20:14 UTC
2019f4e0ddb3f7c0d3246042ee7535b7348792ce
3 files changed
+30
hw/arm/Kconfig
+1
@@ -731,4 +731,5 @@ config AXIADO_SOC
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select ARM_GIC
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select CADENCE # UART
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select AXIADO_CLK
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+ select AXIADO_SDHCI
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select UNIMP
hw/arm/ax3000-soc.c
+22
@@ -35,6 +35,7 @@ static void ax3000_init(Object *obj)
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}
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object_initialize_child(obj, "clk", &s->ax3000_clk, TYPE_AX3000_CLK);
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+ object_initialize_child(obj, "sdhci0", &s->sdhci0, TYPE_AXIADO_SDHCI);
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}
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static void ax3000_realize(DeviceState *dev, Error **errp)
@@ -46,6 +47,7 @@ static void ax3000_realize(DeviceState *dev, Error **errp)
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QList *redist_region_count;
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SysBusDevice *sdhci0_sbd;
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DeviceState *card;
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+ DriveInfo *dinfo;
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/* CPUs */
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for (int i = 0; i < sc->num_cpus; i++) {
@@ -165,6 +167,26 @@ static void ax3000_realize(DeviceState *dev, Error **errp)
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ax3000_clk), 0, AX3000_PLL_BASE);
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+
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+ /* SDHCI */
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+ sdhci0_sbd = SYS_BUS_DEVICE(&s->sdhci0);
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+ if (!sysbus_realize(sdhci0_sbd, errp)) {
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+ return;
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+ }
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+
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+ sysbus_mmio_map(sdhci0_sbd, 0, AX3000_SDHCI0_BASE);
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+ sysbus_mmio_map(sdhci0_sbd, 1, AX3000_EMMC_PHY_BASE);
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+ sysbus_connect_irq(sdhci0_sbd, 0,
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+ qdev_get_gpio_in(gic_dev, AX3000_SDHCI0_IRQ));
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+
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+ dinfo = drive_get(IF_SD, 0, 0);
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+ if (dinfo) {
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+ card = qdev_new(TYPE_SD_CARD);
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+ qdev_prop_set_drive_err(card, "drive",
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+ blk_by_legacy_dinfo(dinfo),
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+ &error_fatal);
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+ qdev_realize_and_unref(card, s->sdhci0.sd_bus, &error_fatal);
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+ }
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}
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static void ax3000_class_init(ObjectClass *oc, const void *data)
include/hw/arm/ax3000-soc.h
+7
@@ -13,6 +13,7 @@
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/char/cadence_uart.h"
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#include "hw/misc/axiado_clk.h"
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+#include "hw/sd/axiado_sdhci.h"
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#include "hw/core/sysbus.h"
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#include "qemu/units.h"
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@@ -34,6 +35,9 @@ OBJECT_DECLARE_TYPE(Ax3000SoCState, Ax3000SoCClass, AX3000_SOC)
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#define AX3000_UART2_BASE 0x80620000
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#define AX3000_UART3_BASE 0x80520800
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+#define AX3000_SDHCI0_BASE 0x86000000
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+#define AX3000_EMMC_PHY_BASE 0x80801C00
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+
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#define AX3000_TIMER_CTRL 0x8A020000
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#define AX3000_PLL_BASE 0x80000000
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@@ -52,6 +56,7 @@ typedef struct Ax3000SoCState {
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MemoryRegion dram[AX3000_NUM_BANKS];
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Ax3000ClkState ax3000_clk;
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CadenceUARTState uart[AX3000_NUM_UARTS];
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+ AxiadoSDHCIState sdhci0;
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} Ax3000SoCState;
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typedef struct Ax3000SoCClass {
@@ -65,6 +70,8 @@ enum Ax3000Irqs {
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AX3000_UART1_IRQ = 113,
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AX3000_UART2_IRQ = 114,
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AX3000_UART3_IRQ = 170,
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+
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+ AX3000_SDHCI0_IRQ = 123,
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};
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#endif /* AXIADO_AX3000_H */