@samitouri / QOSamiQemu / commits / 209638d448

target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()

We have a lot of TCG only initialization in the common cpu_reset_hold callback that prevents --disable-tcg to work. Put a CONFIG_TCG ifdef around those bits to make the build work. Eventually we'll create a TCG specific reset function in tcg-cpu.c but for now this suffices. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260703180538.3346781-18-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Daniel Henrique Barboza committed Jul 3, 2026 at 15:05 UTC 209638d4480985d6ce1339fa8627c1d13571eb58

1 file changed +6 -5

target/riscv/cpu.c

+6 -5

@@ -965,10 +965,6 @@ bool riscv_cpu_has_work(CPUState *cs)

965

966 static void riscv_cpu_reset_hold(Object *obj, ResetType type)

967 {

968 -#ifndef CONFIG_USER_ONLY

969 - uint8_t iprio;

970 - int i, irq, rdzero;

971 -#endif

968 CPUState *cs = CPU(obj);

969 RISCVCPU *cpu = RISCV_CPU(cs);

970 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);

@@ -1020,6 +1016,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)

1016 MENVCFG_ADUE : 0);

1017 env->henvcfg = 0;

1018

1019 +#ifdef CONFIG_TCG

1020 + uint8_t iprio;

1021 + int i, irq, rdzero;

1022 +

1023 /* Initialized default priorities of local interrupts. */

1024 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {

1025 iprio = riscv_cpu_default_priority(i);

@@ -1057,11 +1057,12 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)

1057 }

1058

1059 pmp_unlock_entries(env);

1060 +#endif /* ifdef CONFIG_TCG */

1061 #else

1062 env->priv = PRV_U;

1063 env->senvcfg = 0;

1064 env->menvcfg = 0;

1064 -#endif

1065 +#endif /* !CONFIG_USER_ONLY */

1066

1067 /* on reset elp is clear */

1068 env->elp = false;