@samitouri / QOSamiQemu / commits / 20eaf9a54a

target/riscv64: Implement min/max with Zbb

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Richard Henderson committed Aug 11, 2026 at 16:50 UTC 20eaf9a54abde6c55a7dacb5888b1deb8d68eb75
1 file changed +40 -4
tcg/riscv64/tcg-target.c.inc
+40 -4
@@ -233,6 +233,10 @@ typedef enum {
233 OPC_CPOPW = 0x6020101b,
234 OPC_CTZ = 0x60101013,
235 OPC_CTZW = 0x6010101b,
236 + OPC_MAX = 0x0a006033,
237 + OPC_MAXU = 0x0a007033,
238 + OPC_MIN = 0x0a004033,
239 + OPC_MINU = 0x0a005033,
240 OPC_ORN = 0x40006033,
241 OPC_REV8 = 0x6b805013,
242 OPC_ROL = 0x60001033,
@@ -2404,20 +2408,52 @@ static void tcg_out_set_borrow(TCGContext *s)
2408 g_assert_not_reached();
2409 }
2410
2411 +static void tgen_smax(TCGContext *s, TCGType type,
2412 + TCGReg a0, TCGReg a1, TCGReg a2)
2413 +{
2414 + tcg_out_opc_reg(s, OPC_MAX, a0, a1, a2);
2415 +}
2416 +
2417 static const TCGOutOpBinary outop_smax = {
2408 - .base.static_constraint = C_NotImplemented,
2418 + .base.static_constraint = C_Dynamic,
2419 + .base.dynamic_constraint = cset_zbb_rrr,
2420 + .out_rrr = tgen_smax,
2421 };
2422
2423 +static void tgen_smin(TCGContext *s, TCGType type,
2424 + TCGReg a0, TCGReg a1, TCGReg a2)
2425 +{
2426 + tcg_out_opc_reg(s, OPC_MIN, a0, a1, a2);
2427 +}
2428 +
2429 static const TCGOutOpBinary outop_smin = {
2412 - .base.static_constraint = C_NotImplemented,
2430 + .base.static_constraint = C_Dynamic,
2431 + .base.dynamic_constraint = cset_zbb_rrr,
2432 + .out_rrr = tgen_smin,
2433 };
2434
2435 +static void tgen_umax(TCGContext *s, TCGType type,
2436 + TCGReg a0, TCGReg a1, TCGReg a2)
2437 +{
2438 + tcg_out_opc_reg(s, OPC_MAXU, a0, a1, a2);
2439 +}
2440 +
2441 static const TCGOutOpBinary outop_umax = {
2416 - .base.static_constraint = C_NotImplemented,
2442 + .base.static_constraint = C_Dynamic,
2443 + .base.dynamic_constraint = cset_zbb_rrr,
2444 + .out_rrr = tgen_umax,
2445 };
2446
2447 +static void tgen_umin(TCGContext *s, TCGType type,
2448 + TCGReg a0, TCGReg a1, TCGReg a2)
2449 +{
2450 + tcg_out_opc_reg(s, OPC_MINU, a0, a1, a2);
2451 +}
2452 +
2453 static const TCGOutOpBinary outop_umin = {
2420 - .base.static_constraint = C_NotImplemented,
2454 + .base.static_constraint = C_Dynamic,
2455 + .base.dynamic_constraint = cset_zbb_rrr,
2456 + .out_rrr = tgen_umin,
2457 };
2458
2459 static void tgen_xor(TCGContext *s, TCGType type,