target/arm: Remove vcpu_dirty=true assigments in hvf_handle_exception()
Commit 2a425aae0b5 ("target/arm: ensure PSCI register updates are flushed") manually sets %vcpu_dirty in hvf_handle_exception(), but these calls follow calls to cpu_synchronize_state() which itself sets %vcpu_dirty. Better have the generic CPU API handle this, but add a pair of assertions when serializing the accelerator state to be safe. Suggested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260423170229.64655-13-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Philippe Mathieu-Daudé committed
Apr 22, 2026 at 15:45 UTC
21cb38b736ea3b37801ebbd8fcc7e71766e86357
1 file changed
+4
-2
target/arm/hvf/hvf.c
+4
-2
@@ -794,6 +794,8 @@ int hvf_arch_get_registers(CPUState *cpu)
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hv_simd_fp_uchar16_t fpval;
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int i, n;
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+ assert(!cpu->vcpu_dirty);
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+
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for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
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ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val);
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*(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val;
@@ -945,6 +947,8 @@ int hvf_arch_put_registers(CPUState *cpu)
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hv_simd_fp_uchar16_t fpval;
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int i, n;
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+ assert(cpu->vcpu_dirty);
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+
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/*
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* Set SVCR first because changing it will zero out Z/P (including NEON)
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* regs
@@ -2498,7 +2502,6 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)
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/* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
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env->xregs[0] = -1;
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}
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- cpu->vcpu_dirty = true;
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} else {
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trace_hvf_unknown_hvc(env->pc, env->xregs[0]);
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hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1);
@@ -2515,7 +2518,6 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)
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/* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
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env->xregs[0] = -1;
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}
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- cpu->vcpu_dirty = true;
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} else {
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trace_hvf_unknown_smc(env->xregs[0]);
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hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1);