target/arm: Implement FTMOPA (non-widening, FP32)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260713230244.70174-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 11, 2026 at 20:14 UTC
21e726d226e53896a0e6dcbb732b93bcea89115e
5 files changed
+92
target/arm/cpu-features.h
+5
@@ -1590,6 +1590,11 @@ static inline bool isar_feature_aa64_sme_mop4(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMOP4);
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}
1592
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+static inline bool isar_feature_aa64_sme_tmop(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, STMOP);
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+}
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+
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static inline bool isar_feature_aa64_ssve_aes(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, AES);
target/arm/tcg/helper-sme-defs.h
+2
@@ -404,3 +404,5 @@ DEF_HELPER_FLAGS_4(sme_usmop4a_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
404
DEF_HELPER_FLAGS_4(sme_usmop4s_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sme_usmop4a_dh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sme_usmop4s_dh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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+
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+DEF_HELPER_FLAGS_6(sme_ftmopa_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
target/arm/tcg/sme.decode
+10
@@ -1131,3 +1131,13 @@ UMOP4_dh 1010 0001 111. ...0 0000 00.. ..0. 1... @mop4_o3
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1132
USMOP4_sb 1000 0001 000. ...0 1000 00.. ..0. 00.. @mop4_o2
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USMOP4_dh 1010 0001 110. ...0 0000 00.. ..0. 1... @mop4_o3
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+
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+# SME TMOP Sparse outer products
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+
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+&tmop zad zn zm zk idx
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+%tmop_zk 10:3 !function=expand_tmop_zk
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+
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+@tmop_o2 .... .... ... zm:5 ... ... .... idx:2 .. zad:2 \
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+ &tmop zn=%zn_ax2 zk=%tmop_zk
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+
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+FTMOPA_ss 1000 0000 010 ..... 000 ... .... .. 00 .. @tmop_o2
target/arm/tcg/sme_helper.c
+49
@@ -2636,6 +2636,49 @@ void sme_mop4(void *vza, void *vzn, void *vzm, void *fn_opaque,
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}
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}
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+/*
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+ * Sparse outer product, non-widening. ESZ in {16, 32}.
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+ */
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+static void sme_tmop(void *vza, void *vzn, void *vzm, uint64_t *zk,
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+ void *fn_opaque, uint32_t desc, MemOp esz,
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+ void (*fn)(void *, void *, void *, void *))
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+{
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+ intptr_t oprsz = simd_maxsz(desc);
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+ intptr_t index = simd_data(desc);
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+ intptr_t esize = 1 << esz;
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+ intptr_t host_adj = HOST_BIG_ENDIAN ? 8 - esize : 0;
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+ /* Base in bits for op3[index*:csize], csize = (VL * 2) / esize. */
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+ intptr_t ctrl_base = index * oprsz * 2;
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+ /* Create a zero for use with the largest esz. */
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+ uint32_t zero = 0;
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+
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+ for (intptr_t row = 0; row < oprsz; row += esize) {
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+ void *vza_row = vza + tile_vslice_offset(row);
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+
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+ for (intptr_t col = 0; col < oprsz; col += esize) {
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+ void *e2 = vzm + (col ^ host_adj);
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+ void *e3 = vza_row + (col ^ host_adj);
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+
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+ /*
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+ * Two control bits select one element:
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+ * Zn[row], if [0] is set,
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+ * Zn+1[row], if [1] is set,
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+ * 0, otherwise.
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+ * Compute the address of that element.
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+ */
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+ void *e1 = &zero;
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+ uint64_t this_ctrl = extractn(zk, (ctrl_base + 2 * col) >> esz, 2);
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+ if (this_ctrl) {
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+ e1 = vzn + (row ^ host_adj);
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+ if (!(this_ctrl & 1)) {
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+ e1 += sizeof(ARMVectorReg);
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+ }
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+ }
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+ fn(e3, e1, e2, fn_opaque);
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+ }
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+ }
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+}
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+
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static void inner_fmop4a_hh(void *vd, void *vn, void *vm, void *vinfo)
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{
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float16 *d = vd, *n = vn, *m = vm;
@@ -2692,6 +2735,12 @@ void HELPER(sme_fmop4a_ss)(void *vza, void *vzn, void *vzm,
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sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(float32), inner_fmop4a_ss);
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}
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+void HELPER(sme_ftmopa_ss)(void *vza, void *vzn, void *vzm, void *vzk,
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+ float_status *fpst, uint32_t desc)
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+{
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+ sme_tmop(vza, vzn, vzm, vzk, fpst, desc, MO_32, inner_fmop4a_ss);
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+}
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+
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static void inner_fmop4s_ss(void *vd, void *vn, void *vm, void *vinfo)
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{
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float32 *d = vd, *n = vn, *m = vm;
target/arm/tcg/translate-sme.c
+26
@@ -31,6 +31,12 @@
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* Include the generated decoder.
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*/
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+static int expand_tmop_zk(DisasContext *s, int x)
35
+{
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+ /* Pseudocode for 1:K:1:zk. */
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+ return 0b10100 | ((x & 4) << 1) | (x & 3);
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+}
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+
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#include "decode-sme.c.inc"
41
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static bool sme2_zt0_enabled_check(DisasContext *s)
@@ -2132,3 +2138,23 @@ TRANS_FEAT(USMOP4_sb, aa64_sme_mop4, do_mop4_int, a, MO_32,
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a->s ? gen_helper_sme_usmop4s_sb : gen_helper_sme_usmop4a_sb)
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TRANS_FEAT(USMOP4_dh, aa64_sme_mop4_i16i64, do_mop4_int, a, MO_64,
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a->s ? gen_helper_sme_usmop4s_dh : gen_helper_sme_usmop4a_dh)
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+
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+static bool do_tmop_fp(DisasContext *s, arg_tmop *a, MemOp esz,
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+ int e_fpst, gen_helper_gvec_4_ptr *fn)
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+{
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+ if (sme_smza_enabled_check(s)) {
2146
+ int svl = streaming_vec_reg_size(s);
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+ uint32_t desc = simd_desc(svl, svl, a->idx);
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+ TCGv_ptr za = get_tile(s, esz, a->zad);
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+ TCGv_ptr zn = vec_full_reg_ptr(s, a->zn);
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+ TCGv_ptr zm = vec_full_reg_ptr(s, a->zm);
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+ TCGv_ptr zk = vec_full_reg_ptr(s, a->zm);
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+ TCGv_ptr fpst = (e_fpst >= 0 ? fpstatus_ptr(e_fpst) : tcg_env);
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+
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+ fn(za, zn, zm, zk, fpst, tcg_constant_i32(desc));
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+ }
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+ return true;
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+}
2158
+
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+TRANS_FEAT(FTMOPA_ss, aa64_sme_tmop, do_tmop_fp,
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+ a, MO_32, FPST_ZA, gen_helper_sme_ftmopa_ss)