target/hexagon: add GVec overrides for HVX absolute difference
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260807152241.1576334-5-brian.cain@oss.qualcomm.com Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Aug 7, 2026 at 08:22 UTC
234d8cb6f2e95cc5078b232943e47bc4f56170c3
5 files changed
+116
target/hexagon/gen_tcg_hvx.h
+16
@@ -326,6 +326,22 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
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tcg_gen_gvec_mul(MO_16, VdV_off, VuV_off, VvV_off, \
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VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+#define fGEN_TCG_V6_vabsdiffub(SHORTCODE) \
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+ gen_gvec_uabsdiff(MO_8, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vabsdiffuh(SHORTCODE) \
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+ gen_gvec_uabsdiff(MO_16, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vabsdiffh(SHORTCODE) \
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+ gen_gvec_sabsdiff(MO_16, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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+#define fGEN_TCG_V6_vabsdiffw(SHORTCODE) \
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+ gen_gvec_sabsdiff(MO_32, VdV_off, VuV_off, VvV_off, \
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+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
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+
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/* Vector shift right - various forms */
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#define fGEN_TCG_V6_vasrh(SHORTCODE) \
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do { \
target/hexagon/genptr.c
+70
@@ -37,6 +37,76 @@
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#include "genptr.h"
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+static void gen_sabsdiff_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
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+{
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+ TCGv_i32 t = tcg_temp_new_i32();
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+
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+ tcg_gen_sub_i32(t, a, b);
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+ tcg_gen_sub_i32(d, b, a);
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+ tcg_gen_movcond_i32(TCG_COND_LT, d, a, b, d, t);
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+}
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+
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+static void gen_sabsdiff_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
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+{
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+ TCGv_vec t = tcg_temp_new_vec_matching(d);
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+
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+ tcg_gen_smin_vec(vece, t, a, b);
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+ tcg_gen_smax_vec(vece, d, a, b);
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+ tcg_gen_sub_vec(vece, d, d, t);
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+}
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+
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+void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs,
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+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
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+{
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+ static const TCGOpcode vecop_list[] = {
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+ INDEX_op_sub_vec, INDEX_op_smin_vec, INDEX_op_smax_vec, 0
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+ };
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+ static const GVecGen3 ops[4] = {
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+ [MO_16] = { .fniv = gen_sabsdiff_vec,
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+ .fno = gen_helper_gvec_sabsdiff_h,
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+ .opt_opc = vecop_list,
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+ .vece = MO_16 },
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+ [MO_32] = { .fni4 = gen_sabsdiff_i32,
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+ .fniv = gen_sabsdiff_vec,
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+ .fno = gen_helper_gvec_sabsdiff_w,
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+ .opt_opc = vecop_list,
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+ .vece = MO_32 },
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+ };
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+
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+ tcg_debug_assert(vece == MO_16 || vece == MO_32);
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+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &ops[vece]);
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+}
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+
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+static void gen_uabsdiff_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
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+{
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+ TCGv_vec t = tcg_temp_new_vec_matching(d);
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+
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+ tcg_gen_umin_vec(vece, t, a, b);
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+ tcg_gen_umax_vec(vece, d, a, b);
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+ tcg_gen_sub_vec(vece, d, d, t);
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+}
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+
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+void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs,
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+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
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+{
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+ static const TCGOpcode vecop_list[] = {
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+ INDEX_op_sub_vec, INDEX_op_umin_vec, INDEX_op_umax_vec, 0
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+ };
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+ static const GVecGen3 ops[4] = {
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+ [MO_8] = { .fniv = gen_uabsdiff_vec,
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+ .fno = gen_helper_gvec_uabsdiff_b,
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+ .opt_opc = vecop_list,
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+ .vece = MO_8 },
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+ [MO_16] = { .fniv = gen_uabsdiff_vec,
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+ .fno = gen_helper_gvec_uabsdiff_h,
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+ .opt_opc = vecop_list,
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+ .vece = MO_16 },
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+ };
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+
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+ tcg_debug_assert(vece == MO_8 || vece == MO_16);
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+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &ops[vece]);
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+}
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+
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TCGv gen_read_reg(TCGv result, int num)
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{
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tcg_gen_mov_tl(result, hex_gpr[num]);
target/hexagon/genptr.h
+4
@@ -59,6 +59,10 @@ TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign);
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void gen_set_half(int N, TCGv result, TCGv src);
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void gen_set_half_i64(int N, TCGv_i64 result, TCGv src);
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void probe_noshuf_load(TCGv va, int s, int mi);
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+void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs,
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+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
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+void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs,
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+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
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extern const target_ulong reg_immut_masks[TOTAL_PER_THREAD_REGS];
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target/hexagon/helper.h
+5
@@ -108,6 +108,11 @@ DEF_HELPER_2(probe_pkt_scalar_store_s0, void, env, int)
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DEF_HELPER_2(probe_hvx_stores, void, env, int)
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DEF_HELPER_2(probe_pkt_scalar_hvx_stores, void, env, int)
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+DEF_HELPER_FLAGS_4(gvec_sabsdiff_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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+DEF_HELPER_FLAGS_4(gvec_sabsdiff_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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+DEF_HELPER_FLAGS_4(gvec_uabsdiff_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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+DEF_HELPER_FLAGS_4(gvec_uabsdiff_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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+
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#if !defined(CONFIG_USER_ONLY)
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DEF_HELPER_3(raise_stack_overflow, void, env, i32, i32)
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DEF_HELPER_2(swi, void, env, i32)
target/hexagon/op_helper.c
+21
@@ -35,6 +35,7 @@
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#include "mmvec/macros.h"
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#include "op_helper.h"
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#include "cpu_helper.h"
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+#include "tcg/tcg-gvec-desc.h"
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#include "translate.h"
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#ifndef CONFIG_USER_ONLY
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#include "hw/hexagon/hexagon_globalreg.h"
@@ -1961,3 +1962,23 @@ void HELPER(pending_interrupt)(CPUHexagonState *env)
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printf("ERROR: bogus helper: " #tag "\n")
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#include "helper_funcs_generated.c.inc"
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+
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+#define DO_ABSDIFF(NAME, TYPE, UTYPE) \
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+void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
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+{ \
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+ intptr_t i, oprsz = simd_oprsz(desc); \
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+ UTYPE *d = vd; \
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+ TYPE *n = vn, *m = vm; \
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+ \
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+ for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
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+ d[i] = n[i] < m[i] ? (UTYPE)m[i] - (UTYPE)n[i] \
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+ : (UTYPE)n[i] - (UTYPE)m[i]; \
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+ } \
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+}
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+
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+DO_ABSDIFF(gvec_sabsdiff_h, int16_t, uint16_t)
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+DO_ABSDIFF(gvec_sabsdiff_w, int32_t, uint32_t)
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+DO_ABSDIFF(gvec_uabsdiff_b, uint8_t, uint8_t)
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+DO_ABSDIFF(gvec_uabsdiff_h, uint16_t, uint16_t)
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+
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+#undef DO_ABSDIFF