@samitouri / QOSamiQemu / commits / 2578f3b68b

tcg/translator: add parameter to translator_loop for current addr type

With TCG_ADDRESS_BITS mechanism, it's now possible to specify which variant every source file is written for. Compared to before, it means that addr_type will now vary per tb translation, where it was constant for a given target previously. Thus, we add new a parameter to translator_loop(). This will allow us to convert targets one by one. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260407222208.271838-15-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Pierrick Bouvier committed Apr 23, 2026 at 10:24 UTC 2578f3b68b2ec8998df8b9e75437e924595e5b55
23 files changed +45 -23
accel/tcg/translate-all.c
-1
@@ -316,7 +316,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s)
316 }
317
318 tcg_ctx->gen_tb = tb;
319 - tcg_ctx->addr_type = target_long_bits() == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
319 tcg_ctx->guest_mo = cpu->cc->tcg_ops->guest_default_memory_order;
320
321 restart_translate:
accel/tcg/translator.c
+3 -1
@@ -121,13 +121,15 @@ bool translator_use_goto_tb(DisasContextBase *db, vaddr dest)
121
122 void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
123 vaddr pc, void *host_pc, const TranslatorOps *ops,
124 - DisasContextBase *db)
124 + DisasContextBase *db, TCGType addr_type)
125 {
126 uint32_t cflags = tb_cflags(tb);
127 TCGOp *icount_start_insn;
128 TCGOp *first_insn_start = NULL;
129 bool plugin_enabled;
130
131 + tcg_ctx->addr_type = addr_type;
132 +
133 /* Initialize DisasContext */
134 db->tb = tb;
135 db->pc_first = pc;
include/exec/translator.h
+3 -1
@@ -20,6 +20,7 @@
20
21 #include "exec/memop.h"
22 #include "exec/vaddr.h"
23 +#include "tcg/tcg.h"
24
25 /**
26 * DisasJumpType:
@@ -132,6 +133,7 @@ typedef struct TranslatorOps {
133 * @host_pc: host physical program counter address
134 * @ops: Target-specific operations.
135 * @db: Disassembly context.
136 + * @addr_type: TCG Type for addresses (TCG_TYPE_VA).
137 *
138 * Generic translator loop.
139 *
@@ -147,7 +149,7 @@ typedef struct TranslatorOps {
149 */
150 void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
151 vaddr pc, void *host_pc, const TranslatorOps *ops,
150 - DisasContextBase *db);
152 + DisasContextBase *db, TCGType addr_type);
153
154 /**
155 * translator_use_goto_tb
target/alpha/translate.c
+2 -1
@@ -2953,5 +2953,6 @@ void alpha_translate_code(CPUState *cpu, TranslationBlock *tb,
2953 int *max_insns, vaddr pc, void *host_pc)
2954 {
2955 DisasContext dc;
2956 - translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base);
2956 + translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base,
2957 + TCG_TYPE_VA);
2958 }
target/arm/tcg/translate-a64.c
+2 -1
@@ -10956,5 +10956,6 @@ void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,
10956 {
10957 DisasContext dc = {};
10958 translator_loop(cpu, tb, max_insns, pc, host_pc,
10959 - &aarch64_translator_ops, &dc.base);
10959 + &aarch64_translator_ops, &dc.base,
10960 + TCG_TYPE_VA);
10961 }
target/arm/tcg/translate.c
+1 -1
@@ -6889,6 +6889,6 @@ void arm_translate_code(CPUState *cpu, TranslationBlock *tb,
6889 (EX_TBFLAG_AM32(tb_flags, THUMB)
6890 ? &thumb_translator_ops
6891 : &arm_translator_ops),
6892 - &dc.base);
6892 + &dc.base, TCG_TYPE_VA);
6893 }
6894 }
target/avr/translate.c
+2 -1
@@ -2802,5 +2802,6 @@ void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb,
2802 int *max_insns, vaddr pc, void *host_pc)
2803 {
2804 DisasContext dc = { };
2805 - translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base);
2805 + translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base,
2806 + TCG_TYPE_VA);
2807 }
target/hexagon/translate.c
+2 -1
@@ -1077,7 +1077,8 @@ void hexagon_translate_code(CPUState *cs, TranslationBlock *tb,
1077 DisasContext ctx;
1078
1079 translator_loop(cs, tb, max_insns, pc, host_pc,
1080 - &hexagon_tr_ops, &ctx.base);
1080 + &hexagon_tr_ops, &ctx.base,
1081 + TCG_TYPE_VA);
1082 }
1083
1084 #define NAME_LEN 64
target/hppa/translate.c
+2 -1
@@ -4899,5 +4899,6 @@ void hppa_translate_code(CPUState *cs, TranslationBlock *tb,
4899 int *max_insns, vaddr pc, void *host_pc)
4900 {
4901 DisasContext ctx = { };
4902 - translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base);
4902 + translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base,
4903 + TCG_TYPE_VA);
4904 }
target/i386/tcg/translate.c
+2 -1
@@ -3615,5 +3615,6 @@ void x86_translate_code(CPUState *cpu, TranslationBlock *tb,
3615 {
3616 DisasContext dc;
3617
3618 - translator_loop(cpu, tb, max_insns, pc, host_pc, &i386_tr_ops, &dc.base);
3618 + translator_loop(cpu, tb, max_insns, pc, host_pc, &i386_tr_ops, &dc.base,
3619 + TCG_TYPE_VA);
3620 }
target/loongarch/tcg/translate.c
+2 -1
@@ -342,7 +342,8 @@ void loongarch_translate_code(CPUState *cs, TranslationBlock *tb,
342 DisasContext ctx;
343
344 translator_loop(cs, tb, max_insns, pc, host_pc,
345 - &loongarch_tr_ops, &ctx.base);
345 + &loongarch_tr_ops, &ctx.base,
346 + TCG_TYPE_VA);
347 }
348
349 void loongarch_translate_init(void)
target/m68k/translate.c
+2 -1
@@ -6126,7 +6126,8 @@ void m68k_translate_code(CPUState *cpu, TranslationBlock *tb,
6126 int *max_insns, vaddr pc, void *host_pc)
6127 {
6128 DisasContext dc;
6129 - translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base);
6129 + translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base,
6130 + TCG_TYPE_VA);
6131 }
6132
6133 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
target/microblaze/translate.c
+2 -1
@@ -1788,7 +1788,8 @@ void mb_translate_code(CPUState *cpu, TranslationBlock *tb,
1788 int *max_insns, vaddr pc, void *host_pc)
1789 {
1790 DisasContext dc;
1791 - translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base);
1791 + translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base,
1792 + TCG_TYPE_VA);
1793 }
1794
1795 void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
target/mips/tcg/translate.c
+2 -1
@@ -15242,7 +15242,8 @@ void mips_translate_code(CPUState *cs, TranslationBlock *tb,
15242 {
15243 DisasContext ctx;
15244
15245 - translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base);
15245 + translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base,
15246 + TCG_TYPE_VA);
15247 }
15248
15249 void mips_tcg_init(void)
target/or1k/translate.c
+2 -1
@@ -1647,7 +1647,8 @@ void openrisc_translate_code(CPUState *cs, TranslationBlock *tb,
1647 DisasContext ctx;
1648
1649 translator_loop(cs, tb, max_insns, pc, host_pc,
1650 - &openrisc_tr_ops, &ctx.base);
1650 + &openrisc_tr_ops, &ctx.base,
1651 + TCG_TYPE_VA);
1652 }
1653
1654 void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
target/ppc/translate.c
+2 -1
@@ -6719,5 +6719,6 @@ void ppc_translate_code(CPUState *cs, TranslationBlock *tb,
6719 {
6720 DisasContext ctx;
6721
6722 - translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base);
6722 + translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base,
6723 + TCG_TYPE_VA);
6724 }
target/riscv/translate.c
+2 -1
@@ -1440,7 +1440,8 @@ void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
1440 {
1441 DisasContext ctx;
1442
1443 - translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base);
1443 + translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base,
1444 + TCG_TYPE_VA);
1445 }
1446
1447 void riscv_translate_init(void)
target/rx/translate.c
+2 -1
@@ -2270,7 +2270,8 @@ void rx_translate_code(CPUState *cs, TranslationBlock *tb,
2270 {
2271 DisasContext dc;
2272
2273 - translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base);
2273 + translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base,
2274 + TCG_TYPE_VA);
2275 }
2276
2277 #define ALLOC_REGISTER(sym, name) \
target/s390x/tcg/translate.c
+2 -1
@@ -6509,7 +6509,8 @@ void s390x_translate_code(CPUState *cs, TranslationBlock *tb,
6509 {
6510 DisasContext dc;
6511
6512 - translator_loop(cs, tb, max_insns, pc, host_pc, &s390x_tr_ops, &dc.base);
6512 + translator_loop(cs, tb, max_insns, pc, host_pc, &s390x_tr_ops, &dc.base,
6513 + TCG_TYPE_VA);
6514 }
6515
6516 void s390x_restore_state_to_opc(CPUState *cs,
target/sh4/translate.c
+2 -1
@@ -2316,5 +2316,6 @@ void sh4_translate_code(CPUState *cs, TranslationBlock *tb,
2316 {
2317 DisasContext ctx;
2318
2319 - translator_loop(cs, tb, max_insns, pc, host_pc, &sh4_tr_ops, &ctx.base);
2319 + translator_loop(cs, tb, max_insns, pc, host_pc, &sh4_tr_ops, &ctx.base,
2320 + TCG_TYPE_VA);
2321 }
target/sparc/translate.c
+2 -1
@@ -5853,7 +5853,8 @@ void sparc_translate_code(CPUState *cs, TranslationBlock *tb,
5853 {
5854 DisasContext dc = {};
5855
5856 - translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base);
5856 + translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base,
5857 + TCG_TYPE_VA);
5858 }
5859
5860 void sparc_tcg_init(void)
target/tricore/translate.c
+2 -1
@@ -8500,7 +8500,8 @@ void tricore_translate_code(CPUState *cs, TranslationBlock *tb,
8500 {
8501 DisasContext ctx;
8502 translator_loop(cs, tb, max_insns, pc, host_pc,
8503 - &tricore_tr_ops, &ctx.base);
8503 + &tricore_tr_ops, &ctx.base,
8504 + TCG_TYPE_VA);
8505 }
8506
8507 /*
target/xtensa/translate.c
+2 -1
@@ -1233,7 +1233,8 @@ void xtensa_translate_code(CPUState *cpu, TranslationBlock *tb,
1233 {
1234 DisasContext dc = {};
1235 translator_loop(cpu, tb, max_insns, pc, host_pc,
1236 - &xtensa_translator_ops, &dc.base);
1236 + &xtensa_translator_ops, &dc.base,
1237 + TCG_TYPE_VA);
1238 }
1239
1240 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)