target/arm: Implement and enable FEAT_SSVE_FEXPA for -cpu max
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260626164819.770787-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 26, 2026 at 09:48 UTC
272eef0d258c892be0084fe9ae653ee883a4ab96
5 files changed
+23
-6
docs/system/arm/emulation.rst
+1
@@ -176,6 +176,7 @@ the following architecture extensions:
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- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
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- FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit elements)
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- FEAT_SSVE_AES (Streaming SVE Mode Advanced Encryption Standard and 128-bit polynomial multiply long instructions)
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+- FEAT_SSVE_FEXPA (Streaming FEXPA instruction)
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- FEAT_SSVE_FP8DOT2 (SVE2 FP8 2-way dot product to half-precision instructions in Streaming SVE mode)
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- FEAT_SSVE_FP8DOT4 (SVE2 FP8 4-way dot product to single-precision instructions in Streaming SVE mode)
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- FEAT_SSVE_FP8FMA (SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode)
linux-user/aarch64/elfload.c
+1
@@ -174,6 +174,7 @@ abi_ulong get_elf_hwcap(CPUState *cs)
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GET_FEATURE_ID(aa64_f8mm8, ARM_HWCAP_A64_F8MM8);
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GET_FEATURE_ID(aa64_f8mm4, ARM_HWCAP_A64_F8MM4);
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GET_FEATURE_ID(aa64_ssve_aes, ARM_HWCAP_A64_SME_AES);
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+ GET_FEATURE_ID(aa64_ssve_fexpa, ARM_HWCAP_A64_SME_SFEXPA);
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GET_FEATURE_ID(aa64_fprcvt, ARM_HWCAP_A64_FPRCVT);
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return hwcaps;
target/arm/cpu-features.h
+5
@@ -1580,6 +1580,11 @@ static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16);
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}
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+static inline bool isar_feature_aa64_ssve_fexpa(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SFEXPA);
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+}
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+
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static inline bool isar_feature_aa64_ssve_aes(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, AES);
target/arm/tcg/cpu64.c
+1
@@ -1384,6 +1384,7 @@ void aarch64_max_tcg_initfn(Object *obj)
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SET_IDREG(isar, ID_AA64DFR0, t);
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t = GET_IDREG(isar, ID_AA64SMFR0);
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+ t = FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* FEAT_SSVE_FEXPA */
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t = FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* FEAT_SSVE_AES */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* FEAT_SSVE_FP8DOT2 */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* FEAT_SSVE_FP8DOT4 */
target/arm/tcg/translate-sve.c
+15
-6
@@ -1369,12 +1369,21 @@ TRANS_FEAT_NONSTREAMING(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
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*** SVE Integer Misc - Unpredicated Group
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*/
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-static gen_helper_gvec_2 * const fexpa_fns[4] = {
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- NULL, gen_helper_sve_fexpa_h,
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- gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
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-};
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-TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz,
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- fexpa_fns[a->esz], a->rd, a->rn, s->fpcr_ah)
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+static bool trans_FEXPA(DisasContext *s, arg_FEXPA *a)
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+{
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+ static gen_helper_gvec_2 * const fexpa_fns[4] = {
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+ NULL, gen_helper_sve_fexpa_h,
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+ gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
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+ };
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+
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+ if (!dc_isar_feature(aa64_ssve_fexpa, s)) {
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+ if (!dc_isar_feature(aa64_sve, s)) {
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+ return false;
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+ }
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+ s->is_nonstreaming = true;
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+ }
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+ return gen_gvec_ool_zz(s, fexpa_fns[a->esz], a->rd, a->rn, s->fpcr_ah);
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+}
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static gen_helper_gvec_3 * const ftssel_fns[4] = {
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NULL, gen_helper_sve_ftssel_h,