ati-vga: Implement HOST_DATA flush to VRAM
Implement flushing the 128-bit HOST_DATA accumulator to VRAM to enable text rendering in X. Supports all datatypes (monochrome frgd/bkgd, monochrome frgd, and color), however monochrome frgd support is partial and does not properly handle transparency/leave-alone. The flush is broken up into two steps. First, if necessary, expansion of the monochrome bits to the destination color depth. Then the expanded pixels are sent to the ati_2d_do_blt one scanline at a time. ati_2d_do_blt then clips and performs the blit. Signed-off-by: Chad Jablonski <chad@jablonski.xyz> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> [balaton: Fix build without pixman] Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-ID: <8d0d4b52a16f5564e37bbc88496d7ab8d41477ac.1773020351.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Chad Jablonski committed
Mar 9, 2026 at 02:47 UTC
2735701ec957c7893b7bb82590dcf80cdd817bca
4 files changed
+139
-6
hw/display/ati.c
+2
-4
@@ -1037,11 +1037,9 @@ static void ati_mm_write(void *opaque, hwaddr addr,
1037
}
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s->host_data.acc[s->host_data.next++] = data;
1039
if (addr == HOST_DATA_LAST) {
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- qemu_log_mask(LOG_UNIMP, "HOST_DATA finish not yet implemented\n");
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- s->host_data.next = 0;
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+ ati_host_data_finish(s);
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} else if (s->host_data.next >= 4) {
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- qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\n");
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- s->host_data.next = 0;
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+ ati_host_data_flush(s);
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}
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break;
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default:
hw/display/ati_2d.c
+130
-2
@@ -47,6 +47,7 @@ static int ati_bpp_from_datatype(const ATIVGAState *s)
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typedef struct {
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int bpp;
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uint32_t rop3;
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+ bool host_data_active;
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bool left_to_right;
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bool top_to_bottom;
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uint32_t frgd_clr;
@@ -85,6 +86,7 @@ static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx)
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{
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ctx->bpp = ati_bpp_from_datatype(s);
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ctx->rop3 = s->regs.dp_mix & GMC_ROP3_MASK;
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+ ctx->host_data_active = s->host_data.active;
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ctx->left_to_right = s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT;
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ctx->top_to_bottom = s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM;
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ctx->frgd_clr = s->regs.dp_brush_frgd_clr;
@@ -178,9 +180,10 @@ static bool ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_pixman)
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qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n");
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return false;
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}
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- if (vis_src.x > 0x3fff || vis_src.y > 0x3fff ||
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+ if (!ctx->host_data_active &&
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+ (vis_src.x > 0x3fff || vis_src.y > 0x3fff ||
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ctx->src_bits >= ctx->vram_end || ctx->src_bits + vis_src.x +
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- (vis_src.y + vis_dst.height) * ctx->src_stride >= ctx->vram_end) {
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+ (vis_src.y + vis_dst.height) * ctx->src_stride >= ctx->vram_end)) {
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qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
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return false;
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}
@@ -300,8 +303,133 @@ static bool ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_pixman)
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void ati_2d_blt(ATIVGAState *s)
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{
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ATI2DCtx ctx;
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+ uint32_t src_source = s->regs.dp_mix & DP_SRC_SOURCE;
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+
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+ /* Finish any active HOST_DATA blits before starting a new blit */
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+ ati_host_data_finish(s);
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+
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+ if (src_source == DP_SRC_HOST || src_source == DP_SRC_HOST_BYTEALIGN) {
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+ /* Begin a HOST_DATA blit */
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+ s->host_data.active = true;
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+ s->host_data.next = 0;
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+ s->host_data.col = 0;
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+ s->host_data.row = 0;
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+ return;
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+ }
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setup_2d_blt_ctx(s, &ctx);
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if (ati_2d_do_blt(&ctx, s->use_pixman)) {
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ati_set_dirty(&s->vga, &ctx);
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}
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}
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+
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+bool ati_host_data_flush(ATIVGAState *s)
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+{
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+ ATI2DCtx ctx, chunk;
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+ uint32_t fg = s->regs.dp_src_frgd_clr;
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+ uint32_t bg = s->regs.dp_src_bkgd_clr;
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+ unsigned bypp, pix_count, row, col, idx;
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+ uint8_t pix_buf[ATI_HOST_DATA_ACC_BITS * sizeof(uint32_t)];
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+ uint32_t byte_pix_order = s->regs.dp_datatype & DP_BYTE_PIX_ORDER;
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+ uint32_t src_source = s->regs.dp_mix & DP_SRC_SOURCE;
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+ uint32_t src_datatype = s->regs.dp_datatype & DP_SRC_DATATYPE;
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+
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+ if (!s->host_data.active) {
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+ return false;
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+ }
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+ if (src_source != DP_SRC_HOST) {
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+ qemu_log_mask(LOG_GUEST_ERROR,
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+ "host_data_blt: unsupported src_source %x\n", src_source);
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+ return false;
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+ }
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+ if (src_datatype != SRC_MONO_FRGD_BKGD && src_datatype != SRC_MONO_FRGD &&
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+ src_datatype != SRC_COLOR) {
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+ qemu_log_mask(LOG_GUEST_ERROR,
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+ "host_data_blt: undefined src_datatype %x\n",
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+ src_datatype);
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+ return false;
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+ }
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+
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+ setup_2d_blt_ctx(s, &ctx);
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+
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+ if (!ctx.left_to_right || !ctx.top_to_bottom) {
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+ qemu_log_mask(LOG_UNIMP,
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+ "host_data_blt: unsupported blit direction %c%c\n",
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+ ctx.left_to_right ? '>' : '<',
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+ ctx.top_to_bottom ? 'v' : '^');
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+ return false;
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+ }
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+
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+ bypp = ctx.bpp / 8;
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+
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+ if (src_datatype == SRC_COLOR) {
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+ pix_count = ATI_HOST_DATA_ACC_BITS / ctx.bpp;
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+ memcpy(pix_buf, &s->host_data.acc[0], sizeof(s->host_data.acc));
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+ } else {
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+ pix_count = ATI_HOST_DATA_ACC_BITS;
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+ /* Expand monochrome bits to color pixels */
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+ idx = 0;
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+ for (int word = 0; word < 4; word++) {
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+ for (int byte = 0; byte < 4; byte++) {
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+ uint8_t byte_val = s->host_data.acc[word] >> (byte * 8);
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+ for (int i = 0; i < 8; i++) {
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+ bool is_fg = byte_val & BIT(byte_pix_order ? i : 7 - i);
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+ uint32_t color = is_fg ? fg : bg;
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+ stn_he_p(&pix_buf[idx], bypp, color);
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+ idx += bypp;
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+ }
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+ }
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+ }
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+ }
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+
384
+ /* Copy and then modify blit ctx for use in a chunked blit */
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+ chunk = ctx;
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+ chunk.src_bits = pix_buf;
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+ chunk.src.y = 0;
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+ chunk.src_stride = ATI_HOST_DATA_ACC_BITS * bypp;
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+
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+ /* Blit one scanline chunk at a time */
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+ row = s->host_data.row;
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+ col = s->host_data.col;
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+ idx = 0;
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+ DPRINTF("blt %dpx @ row: %d, col: %d\n", pix_count, row, col);
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+ while (idx < pix_count && row < ctx.dst.height) {
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+ unsigned pix_in_scanline = MIN(pix_count - idx,
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+ ctx.dst.width - col);
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+ chunk.src.x = idx;
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+ /* Build a rect for this scanline chunk */
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+ chunk.dst.x = ctx.dst.x + col;
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+ chunk.dst.y = ctx.dst.y + row;
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+ chunk.dst.width = pix_in_scanline;
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+ chunk.dst.height = 1;
404
+ DPRINTF("blt %dpx span @ row: %d, col: %d to dst (%d,%d)\n",
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+ pix_in_scanline, row, col, chunk.dst.x, chunk.dst.y);
406
+ if (ati_2d_do_blt(&chunk, s->use_pixman)) {
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+ ati_set_dirty(&s->vga, &chunk);
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+ }
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+ idx += pix_in_scanline;
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+ col += pix_in_scanline;
411
+ if (col >= ctx.dst.width) {
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+ col = 0;
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+ row += 1;
414
+ }
415
+ }
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+
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+ /* Track state of the overall blit for use by the next flush */
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+ s->host_data.next = 0;
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+ s->host_data.row = row;
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+ s->host_data.col = col;
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+ if (s->host_data.row >= ctx.dst.height) {
422
+ s->host_data.active = false;
423
+ }
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+
425
+ return s->host_data.active;
426
+}
427
+
428
+void ati_host_data_finish(ATIVGAState *s)
429
+{
430
+ if (ati_host_data_flush(s)) {
431
+ qemu_log_mask(LOG_GUEST_ERROR,
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+ "HOST_DATA blit ended before all data was written\n");
433
+ }
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+ s->host_data.active = false;
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+}
hw/display/ati_int.h
+3
@@ -33,6 +33,7 @@
33
34
#define ATI_RAGE128_LINEAR_APER_SIZE (64 * MiB)
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#define ATI_R100_LINEAR_APER_SIZE (128 * MiB)
36
+#define ATI_HOST_DATA_ACC_BITS 128
37
38
#define TYPE_ATI_VGA "ati-vga"
39
OBJECT_DECLARE_SIMPLE_TYPE(ATIVGAState, ATI_VGA)
@@ -128,5 +129,7 @@ struct ATIVGAState {
129
const char *ati_reg_name(int num);
130
131
void ati_2d_blt(ATIVGAState *s);
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+bool ati_host_data_flush(ATIVGAState *s);
133
+void ati_host_data_finish(ATIVGAState *s);
134
135
#endif /* ATI_INT_H */
hw/display/ati_regs.h
+4
@@ -397,7 +397,11 @@
397
#define DST_32BPP 0x00000006
398
#define DP_DST_DATATYPE 0x0000000f
399
#define DP_BRUSH_DATATYPE 0x00000f00
400
+#define SRC_MONO_FRGD_BKGD 0x00000000
401
+#define SRC_MONO_FRGD 0x00010000
402
+#define SRC_COLOR 0x00030000
403
#define DP_SRC_DATATYPE 0x00030000
404
+#define DP_BYTE_PIX_ORDER 0x40000000
405
406
#define BRUSH_SOLIDCOLOR 0x00000d00
407