disas/riscv: Split xthead_opcode_data
Move the table to riscv-xthead-op.c.inc and massage the lines into OP() form. Drop th.illegal as unused. Return pointers to objects directly. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-44-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Richard Henderson committed
Aug 12, 2026 at 15:31 UTC
282d8cca8b8475885c126a82627e783089e7f520
2 files changed
+243
-363
disas/riscv-xthead-op.c.inc
new
+125
@@ -0,0 +1,125 @@
1
+/* XTheadBa */
2
+OP(th_addsl, "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
3
+
4
+/* XTheadBb */
5
+OP(th_srri, "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
6
+OP(th_srriw, "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm)
7
+OP(th_ext, "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
8
+OP(th_extu, "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
9
+OP(th_ff0, "th.ff0", rv_codec_r2, rv_fmt_rd_rs1)
10
+OP(th_ff1, "th.ff1", rv_codec_r2, rv_fmt_rd_rs1)
11
+OP(th_rev, "th.rev", rv_codec_r2, rv_fmt_rd_rs1)
12
+OP(th_revw, "th.revw", rv_codec_r2, rv_fmt_rd_rs1)
13
+OP(th_tstnbz, "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1)
14
+
15
+/* XTheadBs */
16
+OP(th_tst, "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
17
+
18
+/* XTheadCmo */
19
+OP(th_dcache_call, "th.dcache.call", rv_codec_none, rv_fmt_none)
20
+OP(th_dcache_ciall, "th.dcache.ciall", rv_codec_none, rv_fmt_none)
21
+OP(th_dcache_iall, "th.dcache.iall", rv_codec_none, rv_fmt_none)
22
+OP(th_dcache_cpa, "th.dcache.cpa", rv_codec_r, rv_fmt_rs1)
23
+OP(th_dcache_cipa, "th.dcache.cipa", rv_codec_r, rv_fmt_rs1)
24
+OP(th_dcache_ipa, "th.dcache.ipa", rv_codec_r, rv_fmt_rs1)
25
+OP(th_dcache_cva, "th.dcache.cva", rv_codec_r, rv_fmt_rs1)
26
+OP(th_dcache_civa, "th.dcache.civa", rv_codec_r, rv_fmt_rs1)
27
+OP(th_dcache_iva, "th.dcache.iva", rv_codec_r, rv_fmt_rs1)
28
+OP(th_dcache_csw, "th.dcache.csw", rv_codec_r, rv_fmt_rs1)
29
+OP(th_dcache_cisw, "th.dcache.cisw", rv_codec_r, rv_fmt_rs1)
30
+OP(th_dcache_isw, "th.dcache.isw", rv_codec_r, rv_fmt_rs1)
31
+OP(th_dcache_cpal1, "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1)
32
+OP(th_dcache_cval1, "th.dcache.cval1", rv_codec_r, rv_fmt_rs1)
33
+OP(th_icache_iall, "th.icache.iall", rv_codec_none, rv_fmt_none)
34
+OP(th_icache_ialls, "th.icache.ialls", rv_codec_none, rv_fmt_none)
35
+OP(th_icache_ipa, "th.icache.ipa", rv_codec_r, rv_fmt_rs1)
36
+OP(th_icache_iva, "th.icache.iva", rv_codec_r, rv_fmt_rs1)
37
+OP(th_l2cache_call, "th.l2cache.call", rv_codec_none, rv_fmt_none)
38
+OP(th_l2cache_ciall, "th.l2cache.ciall", rv_codec_none, rv_fmt_none)
39
+OP(th_l2cache_iall, "th.l2cache.iall", rv_codec_none, rv_fmt_none)
40
+
41
+/* XTheadCondMov */
42
+OP(th_mveqz, "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
43
+OP(th_mvnez, "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2)
44
+
45
+/* XTheadFMemIdx */
46
+OP(th_flrd, "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
47
+OP(th_flrw, "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
48
+OP(th_flurd, "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
49
+OP(th_flurw, "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
50
+OP(th_fsrd, "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
51
+OP(th_fsrw, "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
52
+OP(th_fsurd, "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
53
+OP(th_fsurw, "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
54
+
55
+/* XTheadFmv */
56
+OP(th_fmv_hw_x, "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1)
57
+OP(th_fmv_x_hw, "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1)
58
+
59
+/* XTheadMac */
60
+OP(th_mula, "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2)
61
+OP(th_mulaw, "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2)
62
+OP(th_mulah, "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2)
63
+OP(th_muls, "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2)
64
+OP(th_mulsw, "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2)
65
+OP(th_mulsh, "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2)
66
+
67
+/* XTheadMemIdx */
68
+OP(th_lbia, "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
69
+OP(th_lbib, "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
70
+OP(th_lbuia, "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
71
+OP(th_lbuib, "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
72
+OP(th_lhia, "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
73
+OP(th_lhib, "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
74
+OP(th_lhuia, "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
75
+OP(th_lhuib, "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
76
+OP(th_lwia, "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
77
+OP(th_lwib, "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
78
+OP(th_lwuia, "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
79
+OP(th_lwuib, "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
80
+OP(th_ldia, "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
81
+OP(th_ldib, "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
82
+OP(th_sbia, "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
83
+OP(th_sbib, "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
84
+OP(th_shia, "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
85
+OP(th_shib, "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
86
+OP(th_swia, "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
87
+OP(th_swib, "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
88
+OP(th_sdia, "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
89
+OP(th_sdib, "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
90
+OP(th_lrb, "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
91
+OP(th_lrbu, "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
92
+OP(th_lrh, "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
93
+OP(th_lrhu, "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
94
+OP(th_lrw, "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
95
+OP(th_lrwu, "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
96
+OP(th_lrd, "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
97
+OP(th_srb, "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
98
+OP(th_srh, "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
99
+OP(th_srw, "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
100
+OP(th_srd, "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
101
+OP(th_lurb, "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
102
+OP(th_lurbu, "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
103
+OP(th_lurh, "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
104
+OP(th_lurhu, "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
105
+OP(th_lurw, "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
106
+OP(th_lurwu, "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
107
+OP(th_lurd, "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
108
+OP(th_surb, "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
109
+OP(th_surh, "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
110
+OP(th_surw, "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
111
+OP(th_surd, "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
112
+
113
+/* XTheadMemPair */
114
+OP(th_ldd, "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm)
115
+OP(th_lwd, "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm)
116
+OP(th_lwud, "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm)
117
+OP(th_sdd, "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm)
118
+OP(th_swd, "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm)
119
+
120
+/* XTheadSync */
121
+OP(th_sfence_vmas, "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2)
122
+OP(th_sync, "th.sync", rv_codec_none, rv_fmt_none)
123
+OP(th_sync_i, "th.sync.i", rv_codec_none, rv_fmt_none)
124
+OP(th_sync_is, "th.sync.is", rv_codec_none, rv_fmt_none)
125
+OP(th_sync_s, "th.sync.s", rv_codec_none, rv_fmt_none)
disas/riscv-xthead.c
+118
-363
@@ -8,248 +8,13 @@
8
#include "disas/riscv.h"
9
#include "disas/riscv-xthead.h"
10
11
-typedef enum {
12
- /* 0 is reserved for rv_op_illegal. */
13
- /* XTheadBa */
14
- rv_op_th_addsl = 1,
15
- /* XTheadBb */
16
- rv_op_th_srri,
17
- rv_op_th_srriw,
18
- rv_op_th_ext,
19
- rv_op_th_extu,
20
- rv_op_th_ff0,
21
- rv_op_th_ff1,
22
- rv_op_th_rev,
23
- rv_op_th_revw,
24
- rv_op_th_tstnbz,
25
- /* XTheadBs */
26
- rv_op_th_tst,
27
- /* XTheadCmo */
28
- rv_op_th_dcache_call,
29
- rv_op_th_dcache_ciall,
30
- rv_op_th_dcache_iall,
31
- rv_op_th_dcache_cpa,
32
- rv_op_th_dcache_cipa,
33
- rv_op_th_dcache_ipa,
34
- rv_op_th_dcache_cva,
35
- rv_op_th_dcache_civa,
36
- rv_op_th_dcache_iva,
37
- rv_op_th_dcache_csw,
38
- rv_op_th_dcache_cisw,
39
- rv_op_th_dcache_isw,
40
- rv_op_th_dcache_cpal1,
41
- rv_op_th_dcache_cval1,
42
- rv_op_th_icache_iall,
43
- rv_op_th_icache_ialls,
44
- rv_op_th_icache_ipa,
45
- rv_op_th_icache_iva,
46
- rv_op_th_l2cache_call,
47
- rv_op_th_l2cache_ciall,
48
- rv_op_th_l2cache_iall,
49
- /* XTheadCondMov */
50
- rv_op_th_mveqz,
51
- rv_op_th_mvnez,
52
- /* XTheadFMemIdx */
53
- rv_op_th_flrd,
54
- rv_op_th_flrw,
55
- rv_op_th_flurd,
56
- rv_op_th_flurw,
57
- rv_op_th_fsrd,
58
- rv_op_th_fsrw,
59
- rv_op_th_fsurd,
60
- rv_op_th_fsurw,
61
- /* XTheadFmv */
62
- rv_op_th_fmv_hw_x,
63
- rv_op_th_fmv_x_hw,
64
- /* XTheadMac */
65
- rv_op_th_mula,
66
- rv_op_th_mulah,
67
- rv_op_th_mulaw,
68
- rv_op_th_muls,
69
- rv_op_th_mulsw,
70
- rv_op_th_mulsh,
71
- /* XTheadMemIdx */
72
- rv_op_th_lbia,
73
- rv_op_th_lbib,
74
- rv_op_th_lbuia,
75
- rv_op_th_lbuib,
76
- rv_op_th_lhia,
77
- rv_op_th_lhib,
78
- rv_op_th_lhuia,
79
- rv_op_th_lhuib,
80
- rv_op_th_lwia,
81
- rv_op_th_lwib,
82
- rv_op_th_lwuia,
83
- rv_op_th_lwuib,
84
- rv_op_th_ldia,
85
- rv_op_th_ldib,
86
- rv_op_th_sbia,
87
- rv_op_th_sbib,
88
- rv_op_th_shia,
89
- rv_op_th_shib,
90
- rv_op_th_swia,
91
- rv_op_th_swib,
92
- rv_op_th_sdia,
93
- rv_op_th_sdib,
94
- rv_op_th_lrb,
95
- rv_op_th_lrbu,
96
- rv_op_th_lrh,
97
- rv_op_th_lrhu,
98
- rv_op_th_lrw,
99
- rv_op_th_lrwu,
100
- rv_op_th_lrd,
101
- rv_op_th_srb,
102
- rv_op_th_srh,
103
- rv_op_th_srw,
104
- rv_op_th_srd,
105
- rv_op_th_lurb,
106
- rv_op_th_lurbu,
107
- rv_op_th_lurh,
108
- rv_op_th_lurhu,
109
- rv_op_th_lurw,
110
- rv_op_th_lurwu,
111
- rv_op_th_lurd,
112
- rv_op_th_surb,
113
- rv_op_th_surh,
114
- rv_op_th_surw,
115
- rv_op_th_surd,
116
- /* XTheadMemPair */
117
- rv_op_th_ldd,
118
- rv_op_th_lwd,
119
- rv_op_th_lwud,
120
- rv_op_th_sdd,
121
- rv_op_th_swd,
122
- /* XTheadSync */
123
- rv_op_th_sfence_vmas,
124
- rv_op_th_sync,
125
- rv_op_th_sync_i,
126
- rv_op_th_sync_is,
127
- rv_op_th_sync_s,
128
-} rv_xthead_op;
129
-
130
-static const rv_opcode_data xthead_opcode_data[] = {
131
- { "th.illegal", rv_codec_illegal, rv_fmt_none },
132
- /* XTheadBa */
133
- { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
134
- /* XTheadBb */
135
- { "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
136
- { "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm },
137
- { "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
138
- { "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
139
- { "th.ff0", rv_codec_r2, rv_fmt_rd_rs1 },
140
- { "th.ff1", rv_codec_r2, rv_fmt_rd_rs1 },
141
- { "th.rev", rv_codec_r2, rv_fmt_rd_rs1 },
142
- { "th.revw", rv_codec_r2, rv_fmt_rd_rs1 },
143
- { "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1 },
144
- /* XTheadBs */
145
- { "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
146
- /* XTheadCmo */
147
- { "th.dcache.call", rv_codec_none, rv_fmt_none },
148
- { "th.dcache.ciall", rv_codec_none, rv_fmt_none },
149
- { "th.dcache.iall", rv_codec_none, rv_fmt_none },
150
- { "th.dcache.cpa", rv_codec_r, rv_fmt_rs1 },
151
- { "th.dcache.cipa", rv_codec_r, rv_fmt_rs1 },
152
- { "th.dcache.ipa", rv_codec_r, rv_fmt_rs1 },
153
- { "th.dcache.cva", rv_codec_r, rv_fmt_rs1 },
154
- { "th.dcache.civa", rv_codec_r, rv_fmt_rs1 },
155
- { "th.dcache.iva", rv_codec_r, rv_fmt_rs1 },
156
- { "th.dcache.csw", rv_codec_r, rv_fmt_rs1 },
157
- { "th.dcache.cisw", rv_codec_r, rv_fmt_rs1 },
158
- { "th.dcache.isw", rv_codec_r, rv_fmt_rs1 },
159
- { "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1 },
160
- { "th.dcache.cval1", rv_codec_r, rv_fmt_rs1 },
161
- { "th.icache.iall", rv_codec_none, rv_fmt_none },
162
- { "th.icache.ialls", rv_codec_none, rv_fmt_none },
163
- { "th.icache.ipa", rv_codec_r, rv_fmt_rs1 },
164
- { "th.icache.iva", rv_codec_r, rv_fmt_rs1 },
165
- { "th.l2cache.call", rv_codec_none, rv_fmt_none },
166
- { "th.l2cache.ciall", rv_codec_none, rv_fmt_none },
167
- { "th.l2cache.iall", rv_codec_none, rv_fmt_none },
168
- /* XTheadCondMov */
169
- { "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2 },
170
- { "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2 },
171
- /* XTheadFMemIdx */
172
- { "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
173
- { "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
174
- { "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
175
- { "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
176
- { "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
177
- { "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
178
- { "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
179
- { "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
180
- /* XTheadFmv */
181
- { "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1 },
182
- { "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1 },
183
- /* XTheadMac */
184
- { "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2 },
185
- { "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
186
- { "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2 },
187
- { "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2 },
188
- { "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
189
- { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
190
- /* XTheadMemIdx */
191
- { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
192
- { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
193
- { "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
194
- { "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
195
- { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
196
- { "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
197
- { "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
198
- { "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
199
- { "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
200
- { "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
201
- { "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
202
- { "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
203
- { "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
204
- { "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
205
- { "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
206
- { "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
207
- { "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
208
- { "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
209
- { "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
210
- { "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
211
- { "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
212
- { "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
213
- { "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
214
- { "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
215
- { "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
216
- { "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
217
- { "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
218
- { "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
219
- { "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
220
- { "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
221
- { "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
222
- { "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
223
- { "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
224
- { "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
225
- { "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
226
- { "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
227
- { "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
228
- { "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
229
- { "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
230
- { "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
231
- { "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
232
- { "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
233
- { "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
234
- { "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
235
- /* XTheadMemPair */
236
- { "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm },
237
- { "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm },
238
- { "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm },
239
- { "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm },
240
- { "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm },
241
- /* XTheadSync */
242
- { "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2 },
243
- { "th.sync", rv_codec_none, rv_fmt_none },
244
- { "th.sync.i", rv_codec_none, rv_fmt_none },
245
- { "th.sync.is", rv_codec_none, rv_fmt_none },
246
- { "th.sync.s", rv_codec_none, rv_fmt_none },
247
-};
11
+#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
12
+#include "riscv-xthead-op.c.inc"
13
+#undef OP
14
15
const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
16
{
17
rv_inst inst = dec->inst;
252
- rv_opcode op = rv_op_illegal;
18
19
switch (((inst >> 0) & 0b11)) {
20
case 3:
@@ -262,7 +27,7 @@ const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
27
case 0b0000000:
28
case 0b0000001:
29
case 0b0000010:
265
- case 0b0000011: op = rv_op_th_addsl; break;
30
+ case 0b0000011: return &op_th_addsl;
31
}
32
break;
33
}
@@ -272,13 +37,12 @@ const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
37
break;
38
}
39
275
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
40
+ return NULL;
41
}
42
43
const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
44
{
45
rv_inst inst = dec->inst;
281
- rv_opcode op = rv_op_illegal;
46
47
switch (((inst >> 0) & 0b11)) {
48
case 3:
@@ -288,41 +52,41 @@ const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
52
switch ((inst >> 12) & 0b111) {
53
case 1:
54
switch ((inst >> 25) & 0b1111111) {
291
- case 0b0001010: op = rv_op_th_srriw; break;
55
+ case 0b0001010: return &op_th_srriw;
56
case 0b1000000:
57
if (((inst >> 20) & 0b11111) == 0) {
294
- op = rv_op_th_tstnbz;
58
+ return &op_th_tstnbz;
59
}
60
break;
61
case 0b1000001:
62
if (((inst >> 20) & 0b11111) == 0) {
299
- op = rv_op_th_rev;
63
+ return &op_th_rev;
64
}
65
break;
66
case 0b1000010:
67
if (((inst >> 20) & 0b11111) == 0) {
304
- op = rv_op_th_ff0;
68
+ return &op_th_ff0;
69
}
70
break;
71
case 0b1000011:
72
if (((inst >> 20) & 0b11111) == 0) {
309
- op = rv_op_th_ff1;
73
+ return &op_th_ff1;
74
}
75
break;
76
case 0b1000100:
77
case 0b1001000:
78
if (((inst >> 20) & 0b11111) == 0) {
315
- op = rv_op_th_revw;
79
+ return &op_th_revw;
80
}
81
break;
82
case 0b0001000:
83
case 0b0001001:
320
- op = rv_op_th_srri;
84
+ return &op_th_srri;
85
break;
86
}
87
break;
324
- case 2: op = rv_op_th_ext; break;
325
- case 3: op = rv_op_th_extu; break;
88
+ case 2: return &op_th_ext;
89
+ case 3: return &op_th_extu;
90
}
91
break;
92
/* custom-0 */
@@ -330,13 +94,12 @@ const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
94
break;
95
}
96
333
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
97
+ return NULL;
98
}
99
100
const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
101
{
102
rv_inst inst = dec->inst;
339
- rv_opcode op = rv_op_illegal;
103
104
switch (((inst >> 0) & 0b11)) {
105
case 3:
@@ -346,7 +109,7 @@ const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
109
switch ((inst >> 12) & 0b111) {
110
case 1:
111
switch ((inst >> 26) & 0b111111) {
349
- case 0b100010: op = rv_op_th_tst; break;
112
+ case 0b100010: return &op_th_tst;
113
}
114
break;
115
}
@@ -356,13 +119,12 @@ const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
119
break;
120
}
121
359
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
122
+ return NULL;
123
}
124
125
const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
126
{
127
rv_inst inst = dec->inst;
365
- rv_opcode op = rv_op_illegal;
128
129
switch (((inst >> 0) & 0b11)) {
130
case 3:
@@ -374,55 +136,55 @@ const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
136
switch ((inst >> 20 & 0b111111111111)) {
137
case 0b000000000001:
138
if (((inst >> 20) & 0b11111) == 0) {
377
- op = rv_op_th_dcache_call;
139
+ return &op_th_dcache_call;
140
}
141
break;
142
case 0b000000000011:
143
if (((inst >> 20) & 0b11111) == 0) {
382
- op = rv_op_th_dcache_ciall;
144
+ return &op_th_dcache_ciall;
145
}
146
break;
147
case 0b000000000010:
148
if (((inst >> 20) & 0b11111) == 0) {
387
- op = rv_op_th_dcache_iall;
149
+ return &op_th_dcache_iall;
150
}
151
break;
390
- case 0b000000101001: op = rv_op_th_dcache_cpa; break;
391
- case 0b000000101011: op = rv_op_th_dcache_cipa; break;
392
- case 0b000000101010: op = rv_op_th_dcache_ipa; break;
393
- case 0b000000100101: op = rv_op_th_dcache_cva; break;
394
- case 0b000000100111: op = rv_op_th_dcache_civa; break;
395
- case 0b000000100110: op = rv_op_th_dcache_iva; break;
396
- case 0b000000100001: op = rv_op_th_dcache_csw; break;
397
- case 0b000000100011: op = rv_op_th_dcache_cisw; break;
398
- case 0b000000100010: op = rv_op_th_dcache_isw; break;
399
- case 0b000000101000: op = rv_op_th_dcache_cpal1; break;
400
- case 0b000000100100: op = rv_op_th_dcache_cval1; break;
152
+ case 0b000000101001: return &op_th_dcache_cpa;
153
+ case 0b000000101011: return &op_th_dcache_cipa;
154
+ case 0b000000101010: return &op_th_dcache_ipa;
155
+ case 0b000000100101: return &op_th_dcache_cva;
156
+ case 0b000000100111: return &op_th_dcache_civa;
157
+ case 0b000000100110: return &op_th_dcache_iva;
158
+ case 0b000000100001: return &op_th_dcache_csw;
159
+ case 0b000000100011: return &op_th_dcache_cisw;
160
+ case 0b000000100010: return &op_th_dcache_isw;
161
+ case 0b000000101000: return &op_th_dcache_cpal1;
162
+ case 0b000000100100: return &op_th_dcache_cval1;
163
case 0b000000010000:
164
if (((inst >> 20) & 0b11111) == 0) {
403
- op = rv_op_th_icache_iall;
165
+ return &op_th_icache_iall;
166
}
167
break;
168
case 0b000000010001:
169
if (((inst >> 20) & 0b11111) == 0) {
408
- op = rv_op_th_icache_ialls;
170
+ return &op_th_icache_ialls;
171
}
172
break;
411
- case 0b000000111000: op = rv_op_th_icache_ipa; break;
412
- case 0b000000110000: op = rv_op_th_icache_iva; break;
173
+ case 0b000000111000: return &op_th_icache_ipa;
174
+ case 0b000000110000: return &op_th_icache_iva;
175
case 0b000000010101:
176
if (((inst >> 20) & 0b11111) == 0) {
415
- op = rv_op_th_l2cache_call;
177
+ return &op_th_l2cache_call;
178
}
179
break;
180
case 0b000000010111:
181
if (((inst >> 20) & 0b11111) == 0) {
420
- op = rv_op_th_l2cache_ciall;
182
+ return &op_th_l2cache_ciall;
183
}
184
break;
185
case 0b000000010110:
186
if (((inst >> 20) & 0b11111) == 0) {
425
- op = rv_op_th_l2cache_iall;
187
+ return &op_th_l2cache_iall;
188
}
189
break;
190
}
@@ -434,13 +196,12 @@ const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
196
break;
197
}
198
437
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
199
+ return NULL;
200
}
201
202
const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
203
{
204
rv_inst inst = dec->inst;
443
- rv_opcode op = rv_op_illegal;
205
206
switch (((inst >> 0) & 0b11)) {
207
case 3:
@@ -450,8 +211,8 @@ const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
211
switch ((inst >> 12) & 0b111) {
212
case 1:
213
switch ((inst >> 25) & 0b1111111) {
453
- case 0b0100000: op = rv_op_th_mveqz; break;
454
- case 0b0100001: op = rv_op_th_mvnez; break;
214
+ case 0b0100000: return &op_th_mveqz;
215
+ case 0b0100001: return &op_th_mvnez;
216
}
217
break;
218
}
@@ -461,13 +222,12 @@ const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
222
break;
223
}
224
464
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
225
+ return NULL;
226
}
227
228
const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
229
{
230
rv_inst inst = dec->inst;
470
- rv_opcode op = rv_op_illegal;
231
232
switch (((inst >> 0) & 0b11)) {
233
case 3:
@@ -477,18 +237,18 @@ const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
237
switch ((inst >> 12) & 0b111) {
238
case 6:
239
switch ((inst >> 27) & 0b11111) {
480
- case 8: op = rv_op_th_flrw; break;
481
- case 10: op = rv_op_th_flurw; break;
482
- case 12: op = rv_op_th_flrd; break;
483
- case 14: op = rv_op_th_flurd; break;
240
+ case 8: return &op_th_flrw;
241
+ case 10: return &op_th_flurw;
242
+ case 12: return &op_th_flrd;
243
+ case 14: return &op_th_flurd;
244
}
245
break;
246
case 7:
247
switch ((inst >> 27) & 0b11111) {
488
- case 8: op = rv_op_th_fsrw; break;
489
- case 10: op = rv_op_th_fsurw; break;
490
- case 12: op = rv_op_th_fsrd; break;
491
- case 14: op = rv_op_th_fsurd; break;
248
+ case 8: return &op_th_fsrw;
249
+ case 10: return &op_th_fsurw;
250
+ case 12: return &op_th_fsrd;
251
+ case 14: return &op_th_fsurd;
252
}
253
break;
254
}
@@ -498,13 +258,12 @@ const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
258
break;
259
}
260
501
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
261
+ return NULL;
262
}
263
264
const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
265
{
266
rv_inst inst = dec->inst;
507
- rv_opcode op = rv_op_illegal;
267
268
switch (((inst >> 0) & 0b11)) {
269
case 3:
@@ -516,12 +275,12 @@ const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
275
switch ((inst >> 25) & 0b1111111) {
276
case 0b1010000:
277
if (((inst >> 20) & 0b11111) == 0) {
519
- op = rv_op_th_fmv_hw_x;
278
+ return &op_th_fmv_hw_x;
279
}
280
break;
281
case 0b1100000:
282
if (((inst >> 20) & 0b11111) == 0) {
524
- op = rv_op_th_fmv_x_hw;
283
+ return &op_th_fmv_x_hw;
284
}
285
break;
286
}
@@ -533,13 +292,12 @@ const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
292
break;
293
}
294
536
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
295
+ return NULL;
296
}
297
298
const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
299
{
300
rv_inst inst = dec->inst;
542
- rv_opcode op = rv_op_illegal;
301
302
switch (((inst >> 0) & 0b11)) {
303
case 3:
@@ -549,12 +307,12 @@ const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
307
switch ((inst >> 12) & 0b111) {
308
case 1:
309
switch ((inst >> 25) & 0b1111111) {
552
- case 0b0010000: op = rv_op_th_mula; break;
553
- case 0b0010001: op = rv_op_th_muls; break;
554
- case 0b0010010: op = rv_op_th_mulaw; break;
555
- case 0b0010011: op = rv_op_th_mulsw; break;
556
- case 0b0010100: op = rv_op_th_mulah; break;
557
- case 0b0010101: op = rv_op_th_mulsh; break;
310
+ case 0b0010000: return &op_th_mula;
311
+ case 0b0010001: return &op_th_muls;
312
+ case 0b0010010: return &op_th_mulaw;
313
+ case 0b0010011: return &op_th_mulsw;
314
+ case 0b0010100: return &op_th_mulah;
315
+ case 0b0010101: return &op_th_mulsh;
316
}
317
break;
318
}
@@ -564,13 +322,12 @@ const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
322
break;
323
}
324
567
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
325
+ return NULL;
326
}
327
328
const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
329
{
330
rv_inst inst = dec->inst;
573
- rv_opcode op = rv_op_illegal;
331
332
switch (((inst >> 0) & 0b11)) {
333
case 3:
@@ -580,54 +337,54 @@ const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
337
switch ((inst >> 12) & 0b111) {
338
case 4:
339
switch ((inst >> 27) & 0b11111) {
583
- case 0: op = rv_op_th_lrb; break;
584
- case 1: op = rv_op_th_lbib; break;
585
- case 2: op = rv_op_th_lurb; break;
586
- case 3: op = rv_op_th_lbia; break;
587
- case 4: op = rv_op_th_lrh; break;
588
- case 5: op = rv_op_th_lhib; break;
589
- case 6: op = rv_op_th_lurh; break;
590
- case 7: op = rv_op_th_lhia; break;
591
- case 8: op = rv_op_th_lrw; break;
592
- case 9: op = rv_op_th_lwib; break;
593
- case 10: op = rv_op_th_lurw; break;
594
- case 11: op = rv_op_th_lwia; break;
595
- case 12: op = rv_op_th_lrd; break;
596
- case 13: op = rv_op_th_ldib; break;
597
- case 14: op = rv_op_th_lurd; break;
598
- case 15: op = rv_op_th_ldia; break;
599
- case 16: op = rv_op_th_lrbu; break;
600
- case 17: op = rv_op_th_lbuib; break;
601
- case 18: op = rv_op_th_lurbu; break;
602
- case 19: op = rv_op_th_lbuia; break;
603
- case 20: op = rv_op_th_lrhu; break;
604
- case 21: op = rv_op_th_lhuib; break;
605
- case 22: op = rv_op_th_lurhu; break;
606
- case 23: op = rv_op_th_lhuia; break;
607
- case 24: op = rv_op_th_lrwu; break;
608
- case 25: op = rv_op_th_lwuib; break;
609
- case 26: op = rv_op_th_lurwu; break;
610
- case 27: op = rv_op_th_lwuia; break;
340
+ case 0: return &op_th_lrb;
341
+ case 1: return &op_th_lbib;
342
+ case 2: return &op_th_lurb;
343
+ case 3: return &op_th_lbia;
344
+ case 4: return &op_th_lrh;
345
+ case 5: return &op_th_lhib;
346
+ case 6: return &op_th_lurh;
347
+ case 7: return &op_th_lhia;
348
+ case 8: return &op_th_lrw;
349
+ case 9: return &op_th_lwib;
350
+ case 10: return &op_th_lurw;
351
+ case 11: return &op_th_lwia;
352
+ case 12: return &op_th_lrd;
353
+ case 13: return &op_th_ldib;
354
+ case 14: return &op_th_lurd;
355
+ case 15: return &op_th_ldia;
356
+ case 16: return &op_th_lrbu;
357
+ case 17: return &op_th_lbuib;
358
+ case 18: return &op_th_lurbu;
359
+ case 19: return &op_th_lbuia;
360
+ case 20: return &op_th_lrhu;
361
+ case 21: return &op_th_lhuib;
362
+ case 22: return &op_th_lurhu;
363
+ case 23: return &op_th_lhuia;
364
+ case 24: return &op_th_lrwu;
365
+ case 25: return &op_th_lwuib;
366
+ case 26: return &op_th_lurwu;
367
+ case 27: return &op_th_lwuia;
368
}
369
break;
370
case 5:
371
switch ((inst >> 27) & 0b11111) {
615
- case 0: op = rv_op_th_srb; break;
616
- case 1: op = rv_op_th_sbib; break;
617
- case 2: op = rv_op_th_surb; break;
618
- case 3: op = rv_op_th_sbia; break;
619
- case 4: op = rv_op_th_srh; break;
620
- case 5: op = rv_op_th_shib; break;
621
- case 6: op = rv_op_th_surh; break;
622
- case 7: op = rv_op_th_shia; break;
623
- case 8: op = rv_op_th_srw; break;
624
- case 9: op = rv_op_th_swib; break;
625
- case 10: op = rv_op_th_surw; break;
626
- case 11: op = rv_op_th_swia; break;
627
- case 12: op = rv_op_th_srd; break;
628
- case 13: op = rv_op_th_sdib; break;
629
- case 14: op = rv_op_th_surd; break;
630
- case 15: op = rv_op_th_sdia; break;
372
+ case 0: return &op_th_srb;
373
+ case 1: return &op_th_sbib;
374
+ case 2: return &op_th_surb;
375
+ case 3: return &op_th_sbia;
376
+ case 4: return &op_th_srh;
377
+ case 5: return &op_th_shib;
378
+ case 6: return &op_th_surh;
379
+ case 7: return &op_th_shia;
380
+ case 8: return &op_th_srw;
381
+ case 9: return &op_th_swib;
382
+ case 10: return &op_th_surw;
383
+ case 11: return &op_th_swia;
384
+ case 12: return &op_th_srd;
385
+ case 13: return &op_th_sdib;
386
+ case 14: return &op_th_surd;
387
+ case 15: return &op_th_sdia;
388
}
389
break;
390
break;
@@ -638,13 +395,12 @@ const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
395
break;
396
}
397
641
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
398
+ return NULL;
399
}
400
401
const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
402
{
403
rv_inst inst = dec->inst;
647
- rv_opcode op = rv_op_illegal;
404
405
switch (((inst >> 0) & 0b11)) {
406
case 3:
@@ -654,15 +410,15 @@ const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
410
switch ((inst >> 12) & 0b111) {
411
case 4:
412
switch ((inst >> 27) & 0b11111) {
657
- case 28: op = rv_op_th_lwd; break;
658
- case 30: op = rv_op_th_lwud; break;
659
- case 31: op = rv_op_th_ldd; break;
413
+ case 28: return &op_th_lwd;
414
+ case 30: return &op_th_lwud;
415
+ case 31: return &op_th_ldd;
416
}
417
break;
418
case 5:
419
switch ((inst >> 27) & 0b11111) {
664
- case 28: op = rv_op_th_swd; break;
665
- case 31: op = rv_op_th_sdd; break;
420
+ case 28: return &op_th_swd;
421
+ case 31: return &op_th_sdd;
422
}
423
break;
424
}
@@ -672,13 +428,12 @@ const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
428
break;
429
}
430
675
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
431
+ return NULL;
432
}
433
434
const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
435
{
436
rv_inst inst = dec->inst;
681
- rv_opcode op = rv_op_illegal;
437
438
switch (((inst >> 0) & 0b11)) {
439
case 3:
@@ -688,13 +443,13 @@ const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
443
switch ((inst >> 12) & 0b111) {
444
case 0:
445
switch ((inst >> 25) & 0b1111111) {
691
- case 0b0000010: op = rv_op_th_sfence_vmas; break;
446
+ case 0b0000010: return &op_th_sfence_vmas;
447
case 0b0000000:
448
switch ((inst >> 20) & 0b11111) {
694
- case 0b11000: op = rv_op_th_sync; break;
695
- case 0b11010: op = rv_op_th_sync_i; break;
696
- case 0b11011: op = rv_op_th_sync_is; break;
697
- case 0b11001: op = rv_op_th_sync_s; break;
449
+ case 0b11000: return &op_th_sync;
450
+ case 0b11010: return &op_th_sync_i;
451
+ case 0b11011: return &op_th_sync_is;
452
+ case 0b11001: return &op_th_sync_s;
453
}
454
break;
455
}
@@ -706,5 +461,5 @@ const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
461
break;
462
}
463
709
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
464
+ return NULL;
465
}