target/ppc: Move st{b, h, w, d, q}cx instructions to decodetree
Move the following store conditional instructions to decodetree specification: stbcx. : X-form sthcx. : X-form stwcx. : X-form stdcx. : X-form stqcx. : X-form The changes were verified by checking that the generated TCG ops remain semantically identical to the legacy translation, using logs captured with the -d in_asm,op flag. Signed-off-by: Utkarsh Verma <uverma@linux.ibm.com> Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-7-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Utkarsh Verma committed
Aug 27, 2026 at 18:59 UTC
29387351e0d4852f58b770aa3ab403099a90e945
3 files changed
+92
-103
target/ppc/insn32.decode
+8
@@ -732,6 +732,14 @@ DSCLIQ 111111 ..... ..... ...... 001000010 . @Z22_tap_sh_rc
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DSCRI 111011 ..... ..... ...... 001100010 . @Z22_ta_sh_rc
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DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
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+### Store Conditional Instructions
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+
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+STBCX 011111 ..... ..... ..... 1010110110 1 @X
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+STHCX 011111 ..... ..... ..... 1011010110 1 @X
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+STWCX 011111 ..... ..... ..... 0010010110 1 @X
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+STDCX 011111 ..... ..... ..... 0011010110 1 @X
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+STQCX 011111 ..... ..... ..... 0010110110 1 @X
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+
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## Vector Exclusive-OR-based Instructions
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VPMSUMD 000100 ..... ..... ..... 10011001000 @VX
target/ppc/translate.c
-103
@@ -3153,104 +3153,6 @@ static void gen_stdat(DisasContext *ctx)
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}
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#endif
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-static void gen_conditional_store(DisasContext *ctx, MemOp memop)
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-{
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- TCGLabel *lfail;
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- TCGv EA;
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- TCGv cr0;
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- TCGv t0;
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- int rs = rS(ctx->opcode);
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-
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- lfail = gen_new_label();
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- EA = tcg_temp_new();
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- cr0 = tcg_temp_new();
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- t0 = tcg_temp_new();
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-
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- tcg_gen_mov_tl(cr0, cpu_so);
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- gen_set_access_type(ctx, ACCESS_RES);
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- gen_addr_reg_index(ctx, EA);
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- tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail);
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- tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail);
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-
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- tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
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- cpu_gpr[rs], ctx->mem_idx,
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- DEF_MEMOP(memop) | MO_ALIGN);
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- tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
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- tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
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- tcg_gen_or_tl(cr0, cr0, t0);
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-
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- gen_set_label(lfail);
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- tcg_gen_trunc_tl_i32(cpu_crf[0], cr0);
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- tcg_gen_movi_tl(cpu_reserve, -1);
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-}
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-
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-#define STCX(name, memop) \
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-static void gen_##name(DisasContext *ctx) \
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-{ \
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- gen_conditional_store(ctx, memop); \
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-}
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-
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-STCX(stbcx_, MO_UB)
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-STCX(sthcx_, MO_UW)
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-STCX(stwcx_, MO_UL)
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-
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-#if defined(TARGET_PPC64)
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-/* stdcx. */
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-STCX(stdcx_, MO_UQ)
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-
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-/* stqcx. */
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-static void gen_stqcx_(DisasContext *ctx)
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-{
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- TCGLabel *lfail;
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- TCGv EA, t0, t1;
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- TCGv cr0;
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- TCGv_i128 cmp, val;
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- int rs = rS(ctx->opcode);
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-
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- if (unlikely(rs & 1)) {
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- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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- return;
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- }
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-
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- lfail = gen_new_label();
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- EA = tcg_temp_new();
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- cr0 = tcg_temp_new();
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-
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- tcg_gen_mov_tl(cr0, cpu_so);
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- gen_set_access_type(ctx, ACCESS_RES);
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- gen_addr_reg_index(ctx, EA);
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- tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail);
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- tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail);
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-
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- cmp = tcg_temp_new_i128();
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- val = tcg_temp_new_i128();
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-
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- tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val);
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-
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- /* Note that the low part is always in RS+1, even in LE mode. */
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- tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]);
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-
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- tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx,
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- DEF_MEMOP(MO_128 | MO_ALIGN));
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-
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- t0 = tcg_temp_new();
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- t1 = tcg_temp_new();
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- tcg_gen_extr_i128_i64(t1, t0, val);
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-
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- tcg_gen_xor_tl(t1, t1, cpu_reserve_val2);
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- tcg_gen_xor_tl(t0, t0, cpu_reserve_val);
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- tcg_gen_or_tl(t0, t0, t1);
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-
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- tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0);
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- tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
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- tcg_gen_or_tl(cr0, cr0, t0);
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-
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- gen_set_label(lfail);
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- tcg_gen_trunc_tl_i32(cpu_crf[0], cr0);
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- tcg_gen_movi_tl(cpu_reserve, -1);
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-}
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-#endif /* defined(TARGET_PPC64) */
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-
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/* wait */
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static void gen_wait(DisasContext *ctx)
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{
@@ -5886,14 +5788,9 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
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GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
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GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
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-GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
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-GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
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-GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
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#if defined(TARGET_PPC64)
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GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
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-GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
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-GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
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#endif
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/* ISA v3.0 changed the extended opcode from 62 to 30 */
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GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT),
target/ppc/translate/fixedpoint-impl.c.inc
+84
@@ -204,6 +204,90 @@ TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_UQ)
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TRANS64(STQ, do_ldst_quad, true, false);
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TRANS64(PSTQ, do_ldst_quad_PLS_D, true);
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+/* Store Conditional Instructions */
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+
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+static bool do_store_cond(DisasContext *ctx, arg_X *a, MemOp mop)
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+{
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+ TCGLabel *lfail = gen_new_label();
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+ TCGv ea = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
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+ TCGv cr0 = tcg_temp_new();
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+ TCGv t0 = tcg_temp_new();
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+
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+ tcg_gen_mov_tl(cr0, cpu_so);
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+ gen_set_access_type(ctx, ACCESS_RES);
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+
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+ tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_reserve, lfail);
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+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(mop), lfail);
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+
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+ tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
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+ cpu_gpr[a->rt], ctx->mem_idx,
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+ DEF_MEMOP(mop) | MO_ALIGN);
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+ tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
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+ tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
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+ tcg_gen_or_tl(cr0, cr0, t0);
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+
229
+ gen_set_label(lfail);
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+ tcg_gen_trunc_tl_i32(cpu_crf[0], cr0);
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+ tcg_gen_movi_tl(cpu_reserve, -1);
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+ return true;
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+}
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+
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+TRANS_FLAGS2(ATOMIC_ISA206, STBCX, do_store_cond, MO_UB);
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+TRANS_FLAGS2(ATOMIC_ISA206, STHCX, do_store_cond, MO_UW);
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+TRANS(STWCX, do_store_cond, MO_UL);
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+TRANS64(STDCX, do_store_cond, MO_UQ);
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+
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+static bool trans_STQCX(DisasContext *ctx, arg_STQCX *a)
241
+{
242
+ REQUIRE_64BIT(ctx);
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+ REQUIRE_INSNS_FLAGS2(ctx, LSQ_ISA207);
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+#if defined(TARGET_PPC64)
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+ TCGLabel *lfail = gen_new_label();
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+ TCGv ea = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
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+ TCGv t0 = tcg_temp_new();
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+ TCGv t1 = tcg_temp_new();
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+ TCGv cr0 = tcg_temp_new();
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+ TCGv_i128 cmp = tcg_temp_new_i128();
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+ TCGv_i128 val = tcg_temp_new_i128();
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+
253
+ if (unlikely(a->rt & 1)) {
254
+ gen_invalid(ctx);
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+ return true;
256
+ }
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+
258
+ tcg_gen_mov_tl(cr0, cpu_so);
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+ gen_set_access_type(ctx, ACCESS_RES);
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+
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+ tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_reserve, lfail);
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+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail);
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+
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+ tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val);
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+
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+ /* Note that the low part is always in RS+1, even in LE mode. */
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+ tcg_gen_concat_i64_i128(val, cpu_gpr[a->rt + 1], cpu_gpr[a->rt]);
268
+
269
+ tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx,
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+ DEF_MEMOP(MO_128 | MO_ALIGN));
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+
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+ tcg_gen_extr_i128_i64(t1, t0, val);
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+
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+ tcg_gen_xor_tl(t1, t1, cpu_reserve_val2);
275
+ tcg_gen_xor_tl(t0, t0, cpu_reserve_val);
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+ tcg_gen_or_tl(t0, t0, t1);
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+
278
+ tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0);
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+ tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
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+ tcg_gen_or_tl(cr0, cr0, t0);
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+
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+ gen_set_label(lfail);
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+ tcg_gen_trunc_tl_i32(cpu_crf[0], cr0);
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+ tcg_gen_movi_tl(cpu_reserve, -1);
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+#else
286
+ qemu_build_not_reached();
287
+#endif
288
+ return true;
289
+}
290
+
291
/*
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* Fixed-Point Compare Instructions
293
*/