target/arm: GICv5 cpuif: Writes to ICC_APR_EL1 can change IRQ/FIQ
The ICC_APR_EL1 register values change the current running priority, which we use in our calculations in gic_hppi(). Changing them can affect whether we have a HPPI, and so the value of the IRQ/FIQ outputs. We need to trigger an update in the register writefn. Fixes: 9bd90bddb79 ("target/arm: GICv5 cpuif: Signal IRQ or FIQ") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260714091806.3568281-3-peter.maydell@linaro.org
Peter Maydell committed
Jul 20, 2026 at 19:05 UTC
2a9847868fcf5e93671c4d759db685474d2d7342
1 file changed
+1
target/arm/tcg/gicv5-cpuif.c
+1
@@ -495,6 +495,7 @@ static void gic_icc_apr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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GICv5Domain domain = gicv5_logical_domain(env);
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value &= 0xffffffff;
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env->gicv5_cpuif.icc_apr[domain] = value;
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+ gicv5_update_irq_fiq(env);
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}
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static uint64_t gic_icc_apr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)